Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2005-11-10
2008-08-12
Le, Thong Q (Department: 2827)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S196000, C365S230030, C365S189040
Reexamination Certificate
active
07411861
ABSTRACT:
An integrated circuit device includes a RAM block including a plurality of wordlines WL, a plurality of bitlines BL, a plurality of memory cells MC, wordline control circuit, and a data read control circuit, and a data line driver block which drives a plurality of data line groups of a display panel based on data supplied from the RAM block. The data read control circuit reads data for pixels corresponding to the signal lines by N (N is an integer larger than one) times reading in one horizontal scan period 1 H of the display panel. The data line driver block includes first to N-th divided data line driver blocks, each of which drives a different data line group of the data line groups and is disposed along a first direction X in which the bitlines BL extend.
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U.S. Appl. No. 12/000,882, filed on Dec. 18, 2007 in the name of Kodaira et al.
Ito Satoru
Itomi Noboru
Karasawa Junichi
Kawaguchi Shuji
Kodaira Satoru
Le Thong Q
Oliff & Berridg,e PLC
Seiko Epson Corporation
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