Integrated circuit device

Details Integrated circuit device Integrated circuit device

1999-08-25

2001-02-27

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S141000, C327S149000, C327S156000

Reexamination Certificate

active

06194932

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improved delayed lock loop (DLL), which generates a timing signal to internal circuitry that operates at a fixed phase timing relative to an external clock, and to an integrated circuit device, which comprises a DLL circuit, the scale of the circuitry of which can be reduced by omitting a variable delay circuit. The present invention also relates to an integrated circuit device in which a variable delay circuit has been eliminated to make the circuit smaller, and in which the timing signal phases can be more precisely controlled.
2. Description of the Related Art
Recent memory devices are required to operate at speeds in excess of 100 MHz. To achieve this a DLL circuit is fabricated internally, the phase of an external clock is matched up with that of a data output signal, and internal wiring does away with delay characteristic effects, thus holding down access time delays and variations. The system side, which controls the memory device, supplies the memory device with a clock, applies data and addresses in synch with the clock, and accepts output data in synch with the clock.
This applicant proposed a DLL circuit such as this in Application No. 8-339988 dated Dec. 19, 1996.
FIG. 1
depicts an example of a timing signal generator, which uses this DLL circuit.
FIG. 1
depicts an input buffer
1
, to which an external clock CLK is input, and which generates an internal clock N
1
; a variable delay circuit
2
, which delays this internal clock N
1
for a predetermined interval of time, and generates a timing signal N
4
; a frequency divider
4
, which generates a first reference clock N
2
by dividing the interval clock N
1
by 1/N; a variable delay circuit
10
, which delays the first reference clock N
2
; a variable clock N
7
, which is propagated via a dummy data output buffer
6
and a dummy input buffer
7
; a phase comparator
8
, which carries out phase comparison on the first reference clock N
2
divided by the frequency divider
4
; and a delay controller
9
, which is responsive to a detection signal N
8
of the phase comparator
8
, and which generates a delay control signal N
9
, which controls the delay time of the above-described variable delay circuits
2
,
10
. A data output buffer
3
, which is an internal circuit, outputs read data from memory DATA as data output DQ in response to the timing signal N
4
.
The DLL circuit comprises a variable delay circuit
10
, dummy circuits
6
,
7
, phase comparator
8
and delay controller
9
. Then, the delay time of the variable delay circuit
10
is controlled by the phase comparator
8
and delay controller
9
so that the first reference clock N
2
is in phase with the variable clock N
7
. As a result, the phase of the external clock CLK matches up with that of the output N
6
of the dummy data output buffer
6
. Then, because the delay time of the variable delay circuit
2
is also controlled by the same delay control signal N
9
, the data output DQ outputted in response to the timing signal N
4
is synchronized with the phase of the external clock CLK.
The frequency divider
4
shown in
FIG. 1
is provided to prevent an increase in power consumption due to the increasing difficulty in conducting phase comparison in a phase comparator
8
as the frequency of the clock CLK increases. The frequency of the clock CLK is lowered to generate a low-frequency standard clock N
2
, and this standard clock N
2
is used in the feed back loop of the DLL circuit to conduct phase comparison for the low-speed clock. Further, unlike the data output DQ, the output N
6
from a dummy data output buffer
6
is not connected to an external terminal resistance, so the output N
6
amplitude is matched to the internal power supply of the integrated circuit so as to be large amplitude level. Thus, when a high-frequency internal clock N
1
is supplied, a full swing is not possible for the output waveform N
6
in accordance with a rectangular wave clock N
1
, resulting in a triangular wave and in unstable delay characteristics. For this reason, the frequency divided clock N
2
is used in the DLL circuit feedback loop.
When entering data, addresses, or commands, the above mentioned timing signal N
4
is supplied to the respective input buffers instead of the above mentioned data output buffer
3
.
However, a plurality of data output DQ is created in a memory device, requiring that a plurality of sets of the circuits depicted in
FIG. 1
be fabricated in line with this. The input buffer
1
and 1/N frequency divider
4
can be integrated into a common circuit, but two of the variable delay circuits, with their large-scale circuit architectures, must be fabricated for each set of circuits, which means the circuitry depicted in
FIG. 1
would run contrary to the high degree of integration required of a memory device.
Further, in the DLL circuit in
FIG. 1
, the clocks N
1
and N
2
, which have different frequencies, are supplied to the two variable delay circuits
2
and
10
respectively, so the variable delay circuits
2
and
10
have different delay times, even when controlled by the same delay control signal N
9
. In other words, the high-speed clock N
1
is supplied to the variable delay circuit
2
, the power supply voltage drops due to the application of high frequency, and the operating speed of the gate forming the variable delay circuit
2
slows down, prolonging the delay time of the variable delay circuit. By contrast, the divided low-frequency clock N
2
is supplied to the variable delay circuit
10
, resulting in less of a drop in the power supply voltage and in less of a delay in the operating speed of the gate forming the variable delay circuit
10
. The delay time of the variable delay circuit
10
accordingly tends to be shorter than the delay time of the variable delay circuit
2
. This difference in delay time causes the timing signal N
4
phase to be delayed, so that the data output DQ phase does not always match the external clock CLK phase.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide an integrated circuit device (IC), which further simplifies a timing signal generator that utilizes a DLL circuit.
Furthermore, another object of the present invention is to provide a simplified IC by omitting a variable delay circuit from a timing signal generator that utilizes a DLL circuit.
An object of the present invention is to provide an integrated circuit device involving a simpler timing signal generation circuit using a DLL circuit, as well as more precise control of its phases.
Another object of the present invention is to provide an integrated circuit device in which a variable delay circuit has been eliminated to simplify the circuit that generates a timing signal using a DLL circuit, and to more precisely control its phases.
To achieve the above-cited objects, the first aspect of the present invention omits a variable delay circuit (
10
in
FIG. 1
) inside a DLL circuit, and instead, creates a timing synchronization circuit, which generates a second reference clock. The timing synchronization circuit shifts the phase of a first reference clock generated by a frequency divider to the timing of a timing signal generated from the other variable delay circuit so that the second reference clock matches to the timing signal. Then, a phase comparator compares the divided first reference clock to a variable clock that delays the second reference clock, and controls the delay time of the variable delay circuit so that both clocks are in phase. As a result, one variable delay circuit can be omitted, and a DLL circuit that uses a divided clock can be configured.
To achieve the above-described objects, the present invention is an integrated circuit device, which comprises an internal circuitry that operates at a predetermined phase related to a supplied clock, the integrated circuit device comprising: a variable delay circuit, which generates a timing signal to the internal circuitry by delaying the supplied c

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