Integrated circuit design for handling of system management inte

Details Integrated circuit design for handling of system management inte Integrated circuit design for handling of system management inte

1996-09-18

1997-11-04

Harvey, Jack B.

395734, 395309, G06F 918, G06F 946

Patent

active

056849974

ABSTRACT:
An electronic system (100) includes a first integrated circuit (IC) (112) having a card system management interrupt (SMI) output pin (CRDSMI#) and interrupt pins (IRQ3-5), and a logic circuit (1620, 1630) having an output connected to the card SMI pin. This logic circuit further has inputs connected to a first and second set of registers and logic for first and second cards (CARD A,B) respectively. Each of the first and second sets of registers and logic include a first register (CSC REG) having bits set by at least a card event (CDCHG) and a battery condition event (BWARN) respectively. A logic gate (2672) responds to combine the bits from the first register. A second register (INT AND GEN CTRL REG) has a bit (SMIEN) for steering the output of the logic gate (2672) for ordinary interrupt or for system management interrupt purposes depending on the state of the bit (SMIEN). A second integrated circuit (110) has a system management interrupt (SMI#) output pin and SMI circuitry (2370) including a SMI register (2610) connected to events sources eligible for SMI response including the card SMI output of the first integrated circuit. This second IC (110) further has a mask SMI register (2620) connected to the SMI register (2610) to select particular ones of the events sources for SMI response. A logic circuit (2634, 2638) is fed by the SMI register (2610) for combining the selected events sources to supply an internal SMI output (SMIOUT). Other circuits, systems and methods are also disclosed.

REFERENCES:
patent: 4200912 (1980-04-01), Harrington et al.
patent: 5101497 (1992-03-01), Culley et al.
patent: 5175853 (1992-12-01), Kardach et al.
patent: 5276888 (1994-01-01), Kardach et al.
patent: 5410710 (1995-04-01), Sarangdhar et al.
patent: 5535420 (1996-07-01), Kardach et al.
Linley Gwennap, Microprocessor Report, "TI Shows Integrated X86 CPU for Notebooks",vol. 8, No.2. Feb. 14, 1994, pp. 5-7.
ACC Micro, 2066 486/386DX Notebook Enhanced-SL Single Chip AT, Rev. 1.2, Oct. 11, 1993 pp. 1-1-1-10.
Intel, 82365SL DF PC Card Interface Controller, Preliminary, Apr. 1993, pp. 1-76.
Intel486 SL Microprocessor SuperSet System Design Guide, System and Power Management, Chapter 12, 1992, pp. 12-1-12-38.
Intel386 SL Microprocessor SuperSet System Design Guide, System and Power Management, Chapter 14, 1992, pp. 14-1-14-28.
Intel386 SL Microprocessor SuperSet Programmer's Reference Manual, System and Power Management, Chapter 6, 1992, pp. 6-1-6-56.
Intel486 SL Microprocessor SuperSet System Design Guide, System and Power Management, 1992, pp. 13-9-13-11.
82C836 ChipSet, Single-Chip 386SX AT Data Book, Dec. 1990, pp. 1-6, 39-49.
Intel, PCI Local Bus, 82092AA PCI to PCMCIA/Enhanced--IDE Controller, Dec. 1993, pp. 2,3,7-9,20-25,47,55,56,70,78,90,96,97.
Vadem, Vadem VG-230 Sub-Notebook Engine Data Manual, Nov. 1992, pp. 1-5,17-29,58-68.
Western Digital, WD8110/LV System Controller 80486SX/DX PC/AT Compatible Desktop, Laptop, Palmtop, and Pen-Based Computers, Sep. 15, 1993, pp. 1-9, 55-65, 93-126.
ALI, M1709 High Performance VESA/PCI/ISA Notebook Chipset, Product Brief, Jan. 8, 1994.
UMC Super Energy Star Green File, Version 4.0, Preliminary UM8881F/8886F Apr. 15, 1994, pp. 1-3, 11-18, 27-30, 37-42.
UMC Super Energy Star Green File, Version 4.0, Preliminary UM8486F Apr. 15, 1994, pp. 6-8, 21-23, 40-43, 57-60, 70-72, 77-78.
UMC Super Energy Star Green File, Version 4.0, Preliminary UM8365F/8366F Apr. 15, 1994, pp. 1-6, 21-29.
Texas Instruments, TACT83000 AT Chip Set, PC Systems Logic, 1991. pp. 2-27-2-37, 2-48-2-49.
Texas Instruments, TACT84500 EISA Chip Set, Designer's Handbook,Chapter 6, 1991, pp. 6-1-6-17, 6-35-6-37.
VLSI Technology, Inc., Polar Mobile Companion Chip Set, Product Bulletin, Aug. 1993.
VSLI Technology, Inc., Scamp IV Chip Set, Product Bulletin, Oct. 1993.
Texas Instruments, Tiffany Single-Chip System Logic for 386SX/486SLC-Based Palmtop/Subnotebook PCs, User's Guide Preliminary Rev. 1.4, May 1993, pp. 1-5, 14-18, 34,36-38, 42-50.
Intel, Microprocessor and Peripheral Handbook, Vol 1, 1989, pp. 2-259-2-277, 4-667-4-669.
EFAR, EC802G One Chip 32 Bits PC/AT Core Logic, Technical Reference Manual, 1994, pp. 11-13, 32-45, 64-80, 93, 96.
Texas Instruments, TACT84411 Single-Chip 80486, Systems Logic, 1993. pp. 1-1-1-5, 2-1, 2-2, 4-1, 4-33-4-35.

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