Integrated circuit design exhibiting reduced capacitance

Details Integrated circuit design exhibiting reduced capacitance Integrated circuit design exhibiting reduced capacitance

2000-08-31

2001-07-24

Mai, Son (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C257S758000

Reexamination Certificate

active

06266266

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits and particularly to integrated circuits having reduced line capacitance.
BACKGROUND OF THE INVENTION
Read/write memory integrated circuits store data by a process called writing and permit the subsequent retrieval of that data by a process called reading. In a conventional memory circuit, data is stored in a plurality of storage locations arranged as an array of memory cells. Each storage location is identified by an address, which might include both a row identifier and a column identifier. The amount of data that can be stored in the cells of a memory integrated circuit is known as the storage capacity of the circuit. In conventional memory circuits, internal data lines transfer the data to the storage locations during a write cycle and transfer the data from the storage locations during a read cycle.
One specific type of memory circuit is known as a random access memory circuit (“RAM”). Random access memory circuits permit the storage locations to be accessed randomly, and further permit data to be both read from and written to the storage locations of the memory circuit. RAM circuits generally come in two forms. The first form of RAM is known as a static RAM circuit (“SRAM”). A primary characteristic of an SRAM circuit is that the circuit uses latches so that the storage locations of the circuit indefinitely retain the data stored therein, provided power is connected to the circuit. The second form of RAM is known as a dynamic RAM circuit (“DRAM”). A primary characteristic of a DRAM circuit is that the circuit uses charge storing elements, such as capacitors, to retain the stored data in the storage locations, and the circuit must periodically recharge (i.e., refresh) the data in order to retain same.
As will be appreciated by those skilled in the art, prior art memory integrated circuits that require a large number of internal data lines typically have high power requirements, have relatively slow speed, and have generally high power and ground line resistance. This high resistance generates undesirable power supply and ground noise, which limits the speed of the circuits.
Although the present invention shall be shown and described in the form of an embedded DRAM macro, those skilled in the art will appreciate that the principles of the present invention are applicable to memory integrated circuits generally, and more particularly to high speed memory integrated circuits requiring a large number of internal data lines.
Throughout this specification, reference will often be made to inputs, outputs, lines and busses, among other things, that are included within the preferred form of the memory integrated circuit. Throughout this specification, if reference is made to one of these, such as a data line, and that data line is given a particular reference numeral for identification purposes, then another data line given the same reference numeral but with a “B” designation shall be understood to be its complement. For instance, a data line
300
B would be understood to be the complement of data line
300
. Conversely, data line
300
would be the complement of data line
300
B. Generally speaking, if they are not tied together (such as when they are equalized), or if they are not driven to the same logic state for a special purpose, when data line
300
is HIGH, data line
300
B is LOW. Conversely, absent special conditions, when data line
300
is LOW, data line
300
B is HIGH. Those skilled in the art will appreciate this concept and understand this designation hereby incorporated herein by reference.
FIG. 1
illustrates the architecture for a conventional DRAM memory macro. In particular,
FIG. 1
shows an embedded DRAM macro
20
A having a first laterally extending boundary
22
and an associated laterally extending boundary
24
defining an opposite side thereof. Macro
20
A further includes two opposing longitudinally extending boundaries
26
,
28
. DRAM macro
20
A includes a plurality of memory cell arrays or banks
30
, each of which includes a plurality of memory cells (i.e., storage locations). Each memory cell has a unique row and column address for identification purposes.
Column decoder logic circuitry
32
is positioned along the length of, and in close proximity to, boundary
26
. As shown, several column select lines
34
extend laterally from column decoder
32
across macro
20
A and over memory cell banks
30
.
Longitudinally extending bands
36
separate adjacent memory cell banks
30
. Bands
36
each include a plurality of sense amplifiers (not shown). For this reason, bands
36
are generally referred to as sense amp bands by those skilled in the art. As shown in
FIG. 1
, in conventional DRAM macros, data lines
38
, power lines
40
and ground lines
42
extend longitudinally across macro
20
A through sense amp bands
36
. Power lines
40
are generally set at a voltage referred to as Vcc by those skilled in the art, and ground lines
42
are generally set at a voltage referred to as Vss by those skilled in the art.
As just described, in this conventional architecture, the data lines
44
and the power and ground lines
40
,
42
run through the sense amp bands
36
. Further, the column select lines
34
typically run across the memory arrays
30
in a direction generally transverse to the data lines. Although suitable for a variety of applications, this conventional architecture for macro
20
A is not suited for memory circuits having a large number of internal data lines
38
. In particular, only a small number of data lines, perhaps only two to four data lines, can run through each sense amp band
36
. This limitation is due to chip area considerations and the consequential limited width of the sense amp bands
36
. In addition, with respect to this conventional architecture, the power and ground lines
40
,
42
have a relatively high resistance. Notably, because they run through the sense amp bands, the power and ground lines must be relatively narrow, which, in turn, causes them to have a relatively high resistance.
FIG. 2
illustrates a DRAM macro architecture that would accommodate a relatively large number of internal data lines. The DRAM macro architecture shown in
FIG. 2
would include global data lines
44
extending laterally across macro
20
B and over the memory arrays
30
, in a direction generally transverse to the sense amp bands
36
, which extend longitudinally across the macro. Macro
20
B would further include local data lines
46
that extend longitudinally through the sense amp bands
36
and connect with the global data lines
44
. Each of these local data lines
46
would be shared by a predetermined set of the sense amplifiers contained within sense amp bands
36
. Each local data line
46
would be associated with exactly one set of sense amplifiers. Further, each set of sense amplifiers would be associated with exactly only one local data line
46
.
During a read operation, a selected one of the sense amplifiers in one of the sets of sense amplifiers would be enabled by a signal present on its associated column select line
34
. Thereafter, the data stored in the memory cell associated with that selected sense amplifier would be transferred to the local data line
46
connected to that selected sense amplifier. The data then, in turn, would be transferred to a global data line
44
connected to that local data line
46
for subsequent processing by circuit elements positioned external to macro
20
B.
During a write operation, data would be sent from an external circuit element (e.g., microprocessor) to the memory macro
20
B for storage at an address therein. The data first would be transferred from a global data line
44
to a local data line
46
connected thereto. A selected one of the sense amplifiers in one of the sets of sense amplifiers would be enabled by a signal present on its associated column select line
34
. Thereafter, the data present on the local data line
46
connected to the selected sense amplifier would be transferred to th

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