Integrated circuit defect review and classification process

Details Integrated circuit defect review and classification process Integrated circuit defect review and classification process

2001-04-20

2002-04-16

Pham, Hao Q. (Department: 2877)

Optics: measuring and testing

Inspection of flaws or impurities

Surface condition

C356S237500, C356S394000

Reexamination Certificate

active

06373566

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to integrated circuit semiconductor device manufacturing. More specifically, the present invention relates to integrated circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process.
2. State of the Art
Integrated circuit semiconductor devices (IC's) are small electronic circuits formed on the surface of a wafer of semiconductor material, such as silicon, in a manufacturing process referred to as “fabrication”. Once fabricated while in wafer form, IC's are electronically probed to evaluate a variety of their electronic characteristics, subsequently cut from the wafer on which they were formed into discrete IC dice or “chips”, and then further tested and assembled for customer use through various well-known individual die IC testing and packaging techniques, including lead frame packaging, Chip-On-Board (COB) packaging, and flip-chip packaging.
Before being shipped to customers, packaged IC's are generally tested to ensure various functions thereof. Testing typically involves a variety of known test steps, such as pre-grade, burn-in, and final, which test IC's for defects and functionality and grade IC's for speed. As shown in
FIG. 1
, IC's that pass the described testing are generally shipped to customers, while IC's that fail the testing are typically rejected.
The testing standards for a particular IC product are sometimes relaxed as the product “matures” such that IC's previously rejected under strict testing standards may pass the relaxed testing standards. Consequently, reject bins containing previously rejected IC's are sometimes “culled” for IC's that are shippable under relaxed testing standards by testing the rejected IC's again using the relaxed testing standards. Unfortunately, while this “culling” process does retrieve shippable IC's from reject bins, it makes inefficient use of expensive and often limited testing resources by diverting those resources away from testing untested IC's in order to retest previously rejected IC's.
Similarly, as shown in
FIG. 2
, all the IC's from the wafers in a wafer lot typically undergo enhanced reliability testing that is more extensive and strict than normal testing when any of the wafers in the lot are deemed to be unreliable because of fabrication or other process errors. Since a wafer lot typically consists of fifty or more wafers, many of the IC's that undergo the enhanced reliability testing do not require it because they come from wafers that are not deemed unreliable. Performing enhanced reliability testing on IC's that do not need it is inefficient because such testing is typically more time-consuming and uses more resources than normal testing.
Likewise, as shown in
FIG. 3
, a new or special “recipe” for fabricating IC's on wafers is sometimes tested by fabricating some wafers from a wafer lot using the special recipe and other wafers from the wafer lot using a control recipe. IC's from the wafers then typically undergo separate assembly and test procedures so that the test results of IC's fabricated using the special recipe are not mixed with the test results of IC's fabricated using the control recipe, and vice versa. Test reports from the separate test procedures are then used to evaluate the special recipe and to determine whether the IC's are to be shipped to customers, reworked, repaired, retested, or rejected. Unfortunately, because the IC's undergo separate test and assembly procedures, undesirable variables, such as differences in assembly and test equipment, are introduced into the testing of the special recipe. It would be desirable, instead, to be able to assemble and test the IC's using the same assembly and test procedures, and to then sort the IC's and their test results into those IC's fabricated using the special recipe and those IC's fabricated using the control recipe.
As described above, IC's are typically tested for various characteristics before being shipped to customers. For example, as shown in
FIG. 4
, IC's may be graded in test for speed and placed in various bins according to their speed. If a customer subsequently requests a more stringent speed grade, IC's in one of the bins are retested and thereby sorted into IC's that meet the more stringent speed grade and those that do not. While this conventional process sorts the IC's into separate speed grades, it makes inefficient use of expensive and often limited testing resources by diverting those resources away from testing untested IC's in order to retest previously tested IC's.
As described in U.S. Pat. Nos. 5,301,143, 5,294,812, and 5,103,166, some methods have been devised to electronically identify individual IC's. Such methods take place “off” the manufacturing line and involve the use of electrically retrievable ID codes, such as so-called “fuse-ID's”, programmed into individual IC's to identify the IC's. The programming of a fuse ID typically involves selectively blowing an arrangement of fuses and anti-fuses in an IC so that when the fuses or anti-fuses are accessed, they output a selected ID code. Unfortunately, none of these methods addresses the problem of identifying IC's on a manufacturing line which will probably fail during subsequent testing and processing to help minimize the use of processing resources and time.
As can be readily seen, since IC's which are ultimately sold to customers involve extensive testing and subsequent packaging of the IC device, it becomes important to identify potentially defective IC's as early as possible in the manufacturing process to help eliminate associated testing, processing, and packaging costs therewith. In particular, if defects in IC's can be identified early in the manufacturing process before any testing occurs while the IC's are still in wafer form, it is very beneficial in the manufacturing process, particularly, if the defects in the IC's can be identified while the IC's are still in wafer form before any substantial testing has been done of the IC's on the wafer. It is also beneficial to identify and classify the defects of the IC's while in wafer form to determine if the wafer should proceed in the various processes of test, manufacture, and packaging with other wafers in the same manufacturing production lot when the inclusion of a wafer having IC's with numerous defects therein may cause the unnecessary testing of other IC's from other wafers in the manufacturing production lot.
SUMMARY OF THE INVENTION
The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprises the steps of visually inspecting the dice on the wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of the dice on the wafer, and determining if the wafer is acceptable to proceed in the manufacturing process.


REFERENCES:
patent: 4209257 (1980-06-01), Uchiyama et al.
patent: 4376583 (1983-03-01), Alford et al.
patent: 4778745 (1988-10-01), Leung
patent: 4791586 (1988-12-01), Maeda et al.
patent: 5103166 (1992-04-01), Jeon et al.
patent: 5127726 (1992-07-01), Moran
patent: 5240866 (1993-08-01), Friedman et al.
patent: 5294812 (1994-03-01), Hashimoto et al.
patent: 5301143 (1994-04-01), Ohri et al.
patent: 5539752 (1996-07-01), Berezin et al.
patent: 5544256 (1996-08-01), Brecher et al.
patent: 5550372 (1996-08-01), Yasue
patent: 6072574 (2000-06-01), Zeimantz

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