Integrated circuit defect review and classification process

Details Integrated circuit defect review and classification process Integrated circuit defect review and classification process

1997-01-30

2000-06-06

Pham, Hoa Q.

Optics: measuring and testing

Inspection of flaws or impurities

Surface condition

3562375, 356394, 250310, G01N 2100

Patent

active

060725745

ABSTRACT:
The present invention relates to circuit defect detection, classification, and review in the wafer stage of the integrated circuit semiconductor device manufacturing process. The method of processing integrated circuit semiconductor dice on a wafer in a manufacturing process for dice comprising the steps of visually inspecting said dice on said wafer to determine defects thereon, summarizing the number, types, and ranges of sizes of the defects of said dice on said wafer, and determining if said wafer is acceptable to proceed in said manufacturing process.

REFERENCES:
patent: 4209257 (1980-06-01), Uchiyama et al.
patent: 4376583 (1983-03-01), Alford et al.
patent: 4778745 (1988-10-01), Leung
patent: 4791586 (1988-12-01), Maeda et al.
patent: 5103166 (1992-04-01), Jeon et al.
patent: 5127726 (1992-07-01), Moran
patent: 5240866 (1993-08-01), Friedman et al.
patent: 5294812 (1994-03-01), Hashimoto et al.
patent: 5301143 (1994-04-01), Ohri et al.
patent: 5539752 (1996-07-01), Berezin et al.
patent: 5544256 (1996-08-01), Brecher et al.
patent: 5550372 (1996-08-01), Yasue

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