Integrated circuit debugging system

Details Integrated circuit debugging system Integrated circuit debugging system

1999-02-01

2002-06-25

Powell, Mark R. (Department: 2122)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C714S738000

Reexamination Certificate

active

06412104

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit debugging system, and more particularly, to a system for debugging an integrated circuit with bi-directional terminals.
2. Description of the Prior Art
Integrated circuit (IC) debugger or debugging system is commonly used to examine the operation and function of the integrated circuits.
FIG. 1
shows a system block diagram illustrating one of conventional IC debuggers. A test pattern is firstly provided from a memory
12
to a comparator
14
. Subsequently, the provided test pattern is compared with the output from an integrated circuit (IC) under test
16
, and a defective IC is therefore isolated. Unfortunately, due to the uni-directional data flow configuration, this conventional IC debugger
10
can not be adapted to debugging an integrated circuit with bi-directional terminals.
For the foregoing reason, there is a need for an integrated circuit debugging system for checking and debugging the integrated circuits with bi-directional terminals.
SUMMARY OF THE INVENTION
In accordance with the present invention, an integrated circuit debugging system is provided for debugging the integrated circuits with bi-directional terminals. In one embodiment, the system includes a clock unit for providing a clock, and a counter counting responsive to the provided clock for generating address. The system also includes an I/O control memory for storing pin status of an integrated circuit under test corresponding to each of the generated address, and a timing diagram memory for storing fitting value of the integrated circuit corresponding to each of the generated address. A tri-state gate is configured to receive the fitting value from the timing diagram memory, and then a comparator is configured to receive and compare the fitting value of the timing diagram memory and signal from the integrated circuit, wherein the integrated circuit is connected to receive output of the tri-state gate when the tri-state gate is enabled. Further, feedback controller is used to control the address generation of the counter, wherein the feedback controller directs one signal or a number of signals indicative of the compared signal from a terminal or a number of terminals, respectively, of the integrated circuit.


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