Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
2000-08-29
2001-11-13
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S259000
Reexamination Certificate
active
06316979
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to an integrated circuit data latch driver circuit.
BACKGROUND OF THE INVENTION
Many high-speed integrated circuit devices, such as synchronous dynamic random access memories (SDRAM) rely upon clock signals to control the flow of commands, data, addresses, and other signals throughout the devices. Additionally, circuit architectures such as RAMBUS and SLDRAM require individual devices to work in unison even though such parts may individually operate at different speeds. As a result, the ability to control the operation of the device through the generation of local clock signals has become increasingly more important.
Typically, synchronous device operations are initiated at the edges of a clock signal (i.e. transitions from high to low, or low to high logic states). To more precisely control the timing of operations within the device, each period of a clock signal is sometimes divided into several periods so that certain operations do not begin until shortly after a clock edge. One method for controlling the timing of operations within a period of a clock signal uses phase-delayed versions of the clock signal. For example, to divide a clock signal into four sub-periods, phase delayed versions are produced which lag the clock signal by 45, 90 and 180 degrees, respectively. Edges of the phase-delayed clock signals provide signal transitions at the beginning or end of each sub-period which can be used to initiate device operations. An example approach is illustrated in the
FIG. 1
where the timing of operations in a memory device
10
is defined by an externally provided control clock reference signal CCLKREF and an externally provided data clock reference signal DCLKREF. The reference clock signals are generated in a memory controller
11
and transmitted to the memory device over a control clock bus
13
and a data clock bus
14
, respectively. The reference clock signals have identical frequencies, although the control clock reference signal is a continuous signal in the data clock reference signal is a discontinuous signal which does not include a pulse for every CCLKREF period. The delay circuit
20
is provided to delay the control clock reference signal and produce a delayed control clock signal for controlling internal latch circuits
18
and output latches
19
. Likewise, a delay circuit is used to generate a delayed data clock reference signal for controlling input data latches
24
.
Because it is desired to allow some adjustment of the delayed signals, a delay lock loop circuit can be provided in delay circuits
20
and
26
. A conventional multiple output variable delay line circuit can be used to generate multiple delayed signals with increased lag relative to the control clock reference signal. See Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits 31(11):1723-1732, November 1996 for a description of a multiple output variable delay line. The data latch/driver circuits provided in a memory device often operate using multiple clock signals. Because accurate operation of the data latch/driver circuits in a synchronous memory device is critical, latch control signals must be carefully generated. Accurate placement of critical edge transitions of the latch control signals is desired. As such, skew between data latch signals must be reduced. In addition, automatic correction of duty cycle error which may exist in a reference clock signal is desired. By correcting duty cycle error, latch timing will not exhibit duty cycle error received on the reference clock signal.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a circuit which provides data latch driver control signals with very little skew. Further, there is a need in the art for a circuit which provides data latch driver control signals with very little skew and corrects for duty cycle distortion in a timing clock signal.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuits and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A device is described which provides data latch driver signals with little skew between the signals, and can optionally correct for duty cycle error.
In particular, the present invention describes a synchronous memory device comprising a clock signal generator circuit coupled to receive an input clock signal and provide a plurality of phase shifted output signals, and a pulse generator circuit coupled to the clock signal generator circuit for providing first and second output signals having corresponding transitions with minimal skew. The pulse generator circuit comprises a first multiplex circuit coupled to receive a first clock signal and provide a first output signal on a first output node which is coupled to a drain of a first pulldown transistor. The first multiplex circuit is controlled by a second clock signal which is 90 degrees out-of-phase with the first clock signal. A second multiplex circuit is provided and coupled to receive the second clock signal and provide a second output signal on a second output node which is coupled to a drain of a second pulldown transistor. The second multiplex circuit is controlled by the first clock signal.
In another embodiment, a synchronous memory device comprises a clock signal generator circuit coupled to receive a first clock signal and provide a plurality of phase shifted output signals, and a pulse generator circuit coupled to the clock signal generator circuit for providing first and second output signals having corresponding transitions spaced apart by one-half of a period of the first clock signal. The pulse generator circuit comprises a first multiplex circuit coupled to receive the first clock signal and provide a first output signal on a first output node which is coupled to a drain of a first pulldown transistor. The first multiplex circuit is controlled by a second clock signal which is 90 degrees out-of-phase with the first clock signal. A second multiplex circuit is described and coupled to receive a third clock signal which is 180 degrees out-of-phase with the first clock signal and provide a second output signal on a second output node which is coupled to a drain of a second pulldown transistor. The second multiplex circuit is controlled by the second clock signal.
In another embodiment a memory system comprises a memory controller and a synchronous memory device coupled to the memory controller through a data bus for bi-directional data communication in synchronization with a data clock. The synchronous memory device comprises a clock signal generator circuit coupled to receive the data clock signal and provide a plurality of phase shifted output signals, a first pulse generator circuit coupled to the clock signal generator circuit and a second pulse generator circuit coupled to the clock signal generator circuit. The first pulse generator circuit provides first and second output signals having corresponding transitions with minimal skew. The second pulse generator circuit provides first and second output signals having corresponding transitions spaced apart by one-half of a period of the first clock signal.
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paten
Dorsey & Whitney LLP
Lam Tuan T.
Micro)n Technology, Inc.
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