Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2003-06-16
2004-03-23
Pert, Evan (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S690000, C257S734000, C257S787000, C438S017000, C438S018000, C438S106000, C438S108000, C438S127000
Reexamination Certificate
active
06710453
ABSTRACT:
FIELD
This invention relates to the field of integrated circuits. More particularly, this invention relates to integrated circuit design and testing.
BACKGROUND
Integrated circuits that operate at relatively higher clock speeds tend to require a greater amount of electrical current than integrated circuits that operate at relatively lower clock speeds. At the speeds at which many faster integrated circuits operate, the electrical characteristics of the current carrying structures within the integrated circuit tend to inhibit the desired operation of the integrated circuit.
For example, at high clock speeds, the voltage drop of the electrical signal between a power input point on the integrated circuit and the structures that are powered by the electrical signal tends to be too great. In such a circumstance, the voltage of the electrical signals provided to the structures is too low for proper operation of the structures, thus inhibiting reliable operation of the entire integrated circuit.
The voltage drop in such cases is related to the electrical current carried by the electrical conductor between the input point, or contact pad, and the structure, multiplied by the resistance of the electrical conductor. Thus, as the electrical current carried by the electrical conductor increases, and all other factors are held relatively constant, the voltage drop along the electrical conductor also increases, thereby resulting in the low voltage problem referred to above.
These problems have been overcome in part by changing the layout of faster integrated circuits from a wire bond design to a flip chip design. In a wire bond design all of the electrical connections to the integrated circuit, including signal, power, and ground, are made through bonding pads that are located around the peripheral edges of the integrated circuit. Thus, wire bond integrated circuits require relatively longer electrical conductors between the bonding pads and the structures of the integrated circuit that are disposed near the core of the integrated circuit. These longer electrical conductors tend to have a relatively greater total electrical resistance because of their length, and thus exhibit a higher voltage drop according to the formula as given above.
Flip chip integrated circuits, on the other hand, distribute bonding pads for the signal, power, and ground connections across the entire surface of the integrated circuit. In this manner, a given set of power and ground connections can provide electrical power to the structures of the integrated circuit that are disposed within a given proximity to the connections, and the problems associated with voltage drop are alleviated.
Unfortunately, there are other difficulties associated with flip chip integrated circuits. For example, testing an unpackaged flip chip integrated circuit, such as when the integrated circuit is in wafer form during the wafer sort testing, tends to be more difficult than testing a wire bond integrated circuit. One reason for this is that the probe cards required to test a flip chip integrated circuit at wafer sort tend to be more difficult to manufacture and maintain, and thus cost more both in the initial purchase and also over the life of the probe card. Testing wire bond integrated circuits, on the other hand, is relatively easier, and thus cheaper.
What is needed, therefore, is an integrated circuit design that overcomes the problems mentioned above.
SUMMARY
The above and other needs are met by an integrated circuit having circuit structures, including at least one of logic elements and memory elements. A core is disposed at an interior portion of the integrated circuit. The core contains core power contacts and core ground contacts for providing electrical power to the circuit structures during functional operation of the integrated circuit.
A peripheral is disposed at an edge portion of the integrated circuit. The peripheral contains signal contacts for sending and receiving electrical signals between the circuit structures and external circuitry. The peripheral also has peripheral power contacts and peripheral ground contacts for providing electrical power to the circuit structures during testing of the integrated circuit. The peripheral power contacts are redundant to at least some of the core power contacts, and the peripheral ground contacts are redundant to at least some of the core power contacts.
In this manner, the integrated circuit is preferably tested at wafer sort using the signal contacts, power contacts, and ground contacts disposed in the peripheral of the integrated circuit, thus avoiding the expense and other problems associated with flip chip probe cards. However, the integrated circuit is preferably packaged using the power contacts and ground contacts in the core of the integrated circuit, thus avoiding the problems associated with voltage drops between circuit structures disposed in the core of the integrated circuit and power contacts and ground contacts disposed in the peripheral of the integrated circuit.
In various preferred embodiments of the invention, the integrated circuit further comprises packaging for protecting the integrated circuit, and package electrical contacts for making electrical connections to the signal contacts, the core power contacts, and the core ground contacts. In a first alternate embodiment, the package electrical contacts do not make electrical connections to the peripheral power contacts and the peripheral ground contacts. In a second alternate embodiment, the package electrical contacts do make at least one electrical connection to the peripheral power contacts and the peripheral ground contacts. In one embodiment the peripheral power contacts are redundant to all of the core power contacts, and the peripheral ground contacts are redundant to all of the core power contacts.
In further embodiments, signal contacts are also disposed in the core of the integrated circuit. In another embodiment the functional operation of the integrated circuit is conducted at a functional clock speed and the testing of the integrated circuit is conducted at a test clock speed, and the functional clock speed of the integrated circuit is higher than the test clock speed of the integrated circuit. In a most preferred embodiment, the functional operation of the integrated circuit is conducted at a functional clock speed of at least about one hundred megahertz, and the testing of the integrated circuit is conducted at a test clock speed of no more than about ten megahertz.
According to another aspect of the invention there is provided a method of fabricating an integrated circuit. Circuit structures are fabricated, including at least one of logic elements and memory elements. Core power contacts and core ground contacts are fabricated in a core, disposed at an interior portion of the integrated circuit. Signal contacts, peripheral power contacts, and peripheral ground contacts are fabricated in a peripheral, disposed at an edge portion of the integrated circuit. The peripheral power contacts are redundant to at least some of the core power contacts, and the peripheral ground contacts are redundant to at least some of the core power contacts.
The integrated circuit is tested by providing electrical power to the circuit structures with the peripheral power contacts and the peripheral ground contacts. Electrical signals are sent and received between the circuit structures and external circuitry with the signal contacts.
The integrated circuit is packaged by making electrical connections to the core power contacts and the core ground contacts. These electrical connections are for providing electrical power to the circuit structures during functional operation of the integrated circuit. Electrical connections are also made to the signal contacts, for sending and receiving electrical signals between the circuit structures and external circuitry during functional operation of the integrated circuit. The integrated circuit is enclosed in a package to protect the integrated circuit.
REFERENCES:
patent: 627
Wright Peter J.
Zarkesh-Ha Payman
LSI Logic Corporation
Luedeka Neely & Graham PC
Pert Evan
Sarkar Asopk Kumar
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