Integrated circuit comprising means to halt the performance of a

Registers – Coded record sensors – Particular sensor structure

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Details

39518311, 395704, 235438, G06F 1130, G06F 1125

Patent

active

058190236

ABSTRACT:
The integrated circuit comprises a central processing unit, a program memory containing a program of instructions connected to the central processing unit by an address bus, a data bus and lines giving control signals for read and write access to this memory, the instructions being carried out by the central processing unit, and at least one data memory connected to the central processing unit by an address bus, a data bus and lines giving control signals for read and write access to this memory. The circuit comprises breaking means enabling the defining of a combination of conditions pertaining to the values present on two of the buses of the memories and to the values of the control signals for access to at least one of these memories, and halting the performance of the instructions if these conditions are verified. The disclosed device is especially valuable for testing an application program of the integrated circuit.

REFERENCES:
patent: 5126541 (1992-06-01), Shinagawa
patent: 5535331 (1996-07-01), Swoboda et al.
Ken Marti, "Use a Logic Analyzer to Debug Real-Time Software," EDN Electric Design News, vol. 34, No. 8, p. 193 (1989).

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