Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
2000-12-21
2002-07-16
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
active
06420919
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronic circuits, and, more particularly, to the control of the electrical characteristics of an output transistor in an integrated circuit.
BACKGROUND OF THE INVENTION
The present invention relates to output transistors, such as MOS transistors, connected to a data bus and presenting a stray capacitance. In particular, the invention relates to controlling a working point in a low state and control time for passing to the low state of such output transistors.
To aid in understanding,
FIG. 1
shows schematically a conventional output stage
10
of an integrated circuit
20
(implemented with CMOS technology) connected to the input of a data bus
30
of the I2C type. The output stage
10
includes an inverting gate
11
, the output of which drives the gate of an output transistor T
OUT
. The output transistor T
OUT
may be an NMOS transistor, for example. The inverting gate
11
includes a PMOS transistor T
1
and a NMOS transistor T
0
connected by their drains. The source of the PMOS transistor T
1
receives the supply voltage V
cc
of the integrated circuit
20
, and the source of the NMOS transistor T
0
is connected to ground (GND).
The inverting gate
11
receives as an input (i.e., the gates of the transistors T
0
, T
1
receive) Binary data DT
X
to be emitted on bus
30
, and delivers inverted data {overscore (DT)}
X
on the gate G of the output transistor T
OUT
. A bit at 1 at the output of inverting gate
11
corresponds to the application of a voltage V
cc
to the gate of the transistor T
OUT
(i.e., the transistor T
1
is conductive) and a bit at 0 corresponds to the connection of the gate of transistor T
OUT
to ground (i.e., the transistor T
0
is conductive).
The transistor T
OUT
is connected by its drain D to the data transmission line
31
of the bus
30
, and its source S is connected to ground. The bus
30
, as seen from its input, presents a stray capacitance C
BUS
between transmission line
31
and ground. When the transistor T
OUT
is in the OFF state, the line
31
is maintained by default at 1 by a bias or pull-up resistor R
BUS
receiving a bias voltage V
1
. In practice, the voltage V
1
may be equal to V
cc
and is, for example, about 5V.
When the transistor T
OUT
receives a bit at 1 on its gate (i.e., the voltage V
cc
), the transistor T
OUT
becomes conductive, the capacitance C
BUS
discharges and the output of stage
10
passes to 0. The discharge time is designated T
FALL
. An output
0
corresponds to a drain-source voltage V
DS
and a drain-source current I
DS
having stable values designated respectively by V
OL
and I
OL
and defining the working point in the low state of the transistor T
OUT
.
For historical reasons relating to the use of bipolar transistors in input or output stages of integrated circuits, the industrial specifications of I2C buses require a rather low voltage V
OL
on the order of 0.2 to 0.4 V, and a rather high current I
OL
on the order of 0.7 to 3 mA. With MOS technology, such a working point may be achieved only with an NMOS transistor having a gate width W much larger than the gate length L, i.e., a ratio W/L clearly larger than 1.
With the saturation current I
SAT
of a MOS transistor being proportional to the ratio W/L, the transistor T
OUT
is thus traversed by a significant current during its switching, the capacitance C
BUS
discharges almost instantaneously, and the time for passing to 0 T
FALL
is very short. However, the fact that the time T
FALL
is very short generates an undesirable electronic noise in transmission line
31
. It is thus desirable that the time T
FALL
be lengthened to at least about 20 ns.
However, in an output stage
10
as described above, obtaining a rather long time T
FALL
is incompatible with obtaining a low voltage V
OL
and a rather high current I
OL
. As a matter of fact, the discharge of the capacitance C
BUS
is basically provided by the transistor current in the saturated state, or the current I
SAT
. Thus, if the ratio W/L of the transistor is decreased to limit the discharge the current I
SAT
of the capacitance C
BUS
, the voltage V
OL
is increased at the same time as the current I
OL
is decreased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for lengthening the time T
FALL
for passing to zero of an output transistor of the type described above, without modifying its working point V
OL
, I
OL
in the low state.
Another object of the present invention is to provide such an output stage including a controller for controlling the fall time of the output transistor when it is connected to a capacitive data bus.
These objects are achieved by a method of lengthening the time for passing to zero a signal on a terminal of an output transistor of the MOS type connected to a data transmission line presenting a predetermined electric capacitance while keeping a substantially identical working point in the low state of the transistor and where the gate of the transistor is driven by a logic circuit present in an integrated circuit receiving a predetermined supply voltage. The method includes lowering the gate-source bias voltage of the transistor in the conductive state in relation to the gate-source bias that would otherwise appear at the output of the logic circuit. The transistor may be designed with an increased width over length ratio of the gate of the transistor for keeping the initial working point in the low state.
Moreover, the method may include connecting the gate of the transistor to a gate bias circuit. The gate bias circuit may be arranged to reduce the voltage in the high state delivered by the logic circuit on the gate of the transistor. Specifically, the gate bias circuit may include a first MOS transistor substantially identical to the output transistor and arranged as a diode, and a native transistor arranged as a diode and arranged in series with the first MOS transistor. Furthermore, a gate-source bias voltage lower than 2 V may be applied to the output transistor for turning it on.
The present invention also relates to an integrated circuit electrically supplied with a predetermined voltage and including an output MOS transistor, a logic circuit providing an output for driving a gate of the output MOS transistor, and a circuit for biasing the gate of output MOS transistor. Accordingly, the gate-source bias voltage of the transistor is lowered in the conductive state in relation to the gate-source bias voltage that would otherwise be present at the output of the logic circuit.
More specifically, the gate-source bias voltage of the transistor in the conductive state may be lower than 2 V. The bias circuit may be arranged to reduce the voltage in the high state delivered by the logic circuit. Also, the bias circuit may include at least a first MOS transistor arranged as a diode and substantially identical to the output transistor. The bias circuit may also include a native transistor arranged as a diode and in series with the first MOS transistor.
Furthermore, the output transistor may have a width over length ratio of the gate that gives to it a working point in the low state in accordance with the specifications of I2C buses and a fall time of the output signal at least equal to 20 nanoseconds. In practice, the integrated circuit may take the form of an EEPROM memory, for example, and the output stage may be arranged for delivering data read in the memory.
REFERENCES:
patent: 4318014 (1982-03-01), McAlister et al.
patent: 4649292 (1987-03-01), Rusznyak
patent: 4874967 (1989-10-01), Deane
patent: 5023488 (1991-06-01), Gunning
patent: 5050127 (1991-09-01), Mitsumoto et al.
patent: 5216294 (1993-06-01), Ryu
patent: 5973534 (1999-10-01), Singh
Off-Chip Driver for Small Computer System Interface, IBM Technical Disclosure Bulletin, US, IBM Corp., New York, vol. 37, No. 5, May 1, 1994, pp. 239-240, XP000453146, ISSN: 0018-8689.
Bertrand Bertrand
Devin Jean
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Callahan Timothy P.
Jorgenson Lisa K.
Luu An T.
STMicroelectronics S.A.
LandOfFree
Integrated circuit comprising an output transistor with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit comprising an output transistor with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit comprising an output transistor with a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2837699