Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-02-19
2001-01-16
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S144000
Reexamination Certificate
active
06175257
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of integrated circuits, and, more particularly, to an integrated circuit having at least two circuits operating at independent frequencies.
BACKGROUND OF THE INVENTION
A master circuit designates a circuit that may control at least one other circuit, called a slave circuit. The slave circuit performs according to instructions dictated by the master circuit. For example, a state machine may be used to produce control sequences for logic circuits that have specific functions, e.g., counters, memories, and arithmetic logic units. These control sequences may or may not be conditional.
Conventionally, the state machine enables the performance of a sequence of operations for producing control signals for controlling a slave circuit. The frequency of operations of the state machine is generally controlled by a clock signal f
1
. In general, the state machine sends logic commands to the slave circuits by a control bus to which a sequencer and the slave circuits are connected. The logic commands include writing or reading information on a data bus. It is also possible that the sequencer may send a command to a particular slave circuit operating at a frequency f
2
for carrying out at least one operation in parallel.
In general, the state machine does not verify whether a particular slave circuit has received the command to be performed. Accordingly, the state machine limits itself, for example, to sending a command during a time interval in which the state machine is sure that the slave circuit will receive this command.
When the state machine and the slave circuit are synchronous, the state machine may send a command having a determined duration corresponding to a certain number of clock cycles. The synchronization between the state machine and the slave circuit makes it possible to ensure efficient reception. Synchronous refers to when the clock frequencies f
1
and f
2
are identical to or multiples of one another with respect to the clock signals originating from the same clock.
In contrast, when the clock frequency f
1
of the state machine and the clock frequency f
2
of the slave circuit are not synchronous, the reception of the control signal by the slave sequencer may become random. This could lead to malfunctioning of the integrated circuit. Not synchronous, i.e., asynchronous, refers to when the respective clock signals are different or undergo significant fluctuations during operation.
SUMMARY OF THE INVENTION
It is an object of the invention to prevent malfunctioning of an integrated circuit comprising at least one master circuit and one slave circuit operating at independent respective frequencies.
The integrated circuit comprises a master circuit having a clock input for receiving a first clock signal originating from a first clock circuit, and an output for providing a control signal. The control signal is activated during an active edge of the first clock signal. A slave circuit has a control input and a clock input for receiving a second clock signal originating from a second clock circuit. The second clock circuit is independent of the first clock circuit. The integrated circuit further comprises a first register having a clock input for receiving the second clock signal, a data input for storing the control signal during an active edge of the second clock signal, and an output is connected to the control input of the slave circuit. During an active edge of the second clock signal, the first register stores the control signal produced by the master circuit and provides the stored control signal. The signal delivered by the first register is synchronized with the second clock signal.
Preferably, the integrated circuit comprises a second register having a clock input for receiving the clock signal, a data input is connected to the output of the first register for storing the control signal during an active edge of the clock signal, and an output. The master circuit further comprises an information input connected to the output of the second register for receiving the control signal to deactivate the control signal at the output of the master circuit when the control signal received becomes active.
To interrupt sending of the control signal to the slave circuit, the input of the second register is connected to the output of the first register for storing the control signal received by the slave circuit during an active edge of the first clock signal. The second register delivers the stored control signal to the master circuit. The use of the two registers eliminates the difficulties caused by different and independent clock frequencies. Furthermore, the master circuit receives a return of the transmission of its control signal by the second register and the information input. This makes it possible to ascertain that the slave circuit has actually received the control signal.
According to another embodiment, the circuit further comprises a third register having a clock input for receiving the clock signal, a data input is connected to the output of the master circuit for storing the control signal during an active edge of the clock signal, and an output is connected to the input of the first register. The third register is connected between the first register and the master circuit. A fourth register has a clock input for receiving the clock signal, a data input is connected to the output of the first register for storing the stopping signal, and an output is connected to the input of the second register. The fourth register is connected between the first and second registers.
This arrangement primarily makes it possible to prevent a condition known as metastability, i.e., having only a slight margin of stability. This condition occurs during fast transitions of logic states on signals present at the input of the register. The signal at the input of the register must be stabilized and must be presented sufficiently in advance so that the register can store the signal during an active edge of the clock of the register. Otherwise, the stored signal is always erroneous which may lead to malfunctioning of the integrated circuit.
According to yet another embodiment, the circuit further comprises an inverter having one input and one output, wherein the input is connected to the output of the first register. The output of the first register is connected to the control input of the slave circuit. A logic gate has two inputs and one output, wherein a first input is connected to the input of the first register. A second input is connected to the output of the inverter. A fifth register has a clock input for receiving the clock signal. An input is connected to the output of the logic gate for storing the control signal, and an output is connected to the control input of the master circuit.
REFERENCES:
patent: 4160154 (1979-07-01), Jennings
patent: 4495629 (1985-01-01), Zasio et al.
patent: 5291529 (1994-03-01), Crook et al.
patent: 5684982 (1997-11-01), Gates
patent: 0 335 547 A2 (1989-03-01), None
patent: 0 798 630 A1 (1997-03-01), None
Patent Abstracts of Japan, vol. 007, No. 030, Feb. 5, 1983, and JP 57 182837 A (Nippon Victor KK), Nov. 10, 1982.
Patent Abstracts of Japan, vol. 018, No. 364, Jun. 8, 1994, and JP 06 097925 A (Mitsubishi Electric Corp), Apr. 8, 1994.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Nguyen Linh
STMicroelectronics S.A.
Tran Toan
LandOfFree
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