Integrated circuit comprising a latch-up protection circuit in c

Details Integrated circuit comprising a latch-up protection circuit in c Integrated circuit comprising a latch-up protection circuit in c

1987-10-15

1989-01-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307296A, 357 236, 357 42, H01L 2710, W03L 100, H03K 3354, H03K 3013

Patent

active

047989742

ABSTRACT:
An integrated circuit has a storage cell and complementary MOS-circuit technology. A substrate bias voltage generator connects a semiconductor substrate having a well region inserted therein to a substrate bias voltage. In order to avoid latch-up effects, an electronic protection circuit connects a current path, for charging a capacitor of the storage cell, only after a delay time .DELTA.T following a switch-on of the integrated circuit.

REFERENCES:
patent: 4591738 (1986-05-01), Bialas et al.
patent: 4695745 (1987-09-01), Mimoto et al.
patent: 4705966 (1987-11-01), Van Zanten
patent: 4733108 (1988-03-01), Truong
patent: 4736121 (1988-04-01), Cini et al.
Semiconductor Electronics Series 14, "Integrated MOS-Circuits", by H. Weib and K. Horninger, pp. 247-248.
Semiconductor Electronics Series 14, "Integrated MOS-Circuits", by H. Weib and K. Horninger, pp. 111-112.
D. Takacs et al, "Static and Transient Latch-Up Hardness in N-Well CMOS with On-Chip Substrate Bias Generator", IEDM 85, Technical Digest, pp. 504 to 508.

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