Integrated circuit components thereof and manufacturing method

Details Integrated circuit components thereof and manufacturing method Integrated circuit components thereof and manufacturing method

1998-12-31

2003-01-07

Everhart, Caridad (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With specified electrode means

C257S506000, C257S590000, C257S263000, C257S304000, C257S511000

Reexamination Certificate

active

06504232

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method for producing, in the manufacturing of an integrated circuit in a bipolar process, a collector pin and a trench for isolating the semiconductor components comprised in the integrated circuit, and to the collector pin, the trench and tie integrated circuit. The collector pin, the trench and the integrated circuit are primarily intended for radio applications or other high-speed communication where components with good performance characteristics are required.
STATE OF THE ART
Traditionally, when manufacturing integrated circuits, so called LOCOS (Local Oxidation of Silicon) isolation is used in combination with junction isolation, to isolate the components of the integrated circuit; see, for example, J. A. Appels et al, “Local Oxidation of Silicon and its application in Semiconductor Technology,”, Philips Res. Rep. vol. 25, 1970, pp. 118-132.
In the manufacturing of bipolar components for RF-IC (Radio Frequency-Integrated Circuits) applications, it is common to isolate the individual components in the silicon substrate from each other with etched trenches instead; see, for example, U.S. Pat. Nos. 4,139,442, 4,789,885, P. C. Hunt et al., “Process HE: A Highly Advanced Trench Isolated Bipolar Technology for Analogue and Digital Applications”, Proc. IEEE 1988 Custom & Integr. Circuits Conf. Rochester N.Y. May 16-19 1988, and A. Hayasaka et al., “U-Groove Isolation Technique for High Speed Bipolar VLSI's”, Proc. IEDM 1982 p. 62.
The technique of trench isolation has also been used for isolating CMOS components, although to a considerably smaller extent, see for example R. D. Rung et. al, “Deep trench isolated CMOS Devices”, IEDM, Techn. Dig. Paper 9.6, 1982.
By means of a trench, etched deeply into the silicon, and surrounding a semiconductor component, such as, for example, a bipolar transistor, the capacitance between the bottom diffusion layer and the substrate can be reduced substantially. At the same time better isolation between adjacent components is achieved, that is, an increased immunity against cross talk, while the dimensions of the transistor cell may be reduced at the same time.
Another advantage of trench isolation is that the trenches may be made so deep, approx. 5-10 &mgr;m, that they extend through the entire epi-layer of the plate, that is, the active surface layer, all the way down to a heavily doped silicon substrate of low resistance. Thus, the isolating properties and the risk for latch-up are reduced, see for example V. dela Torre et al., “MOSAIC V-A Very High Performance Bipolar Technology”, Proc. BCTM 1991, p. 21.
Below, and in connection with the
FIGS. 1-3
, a commonly used method for making a trench when manufacturing a bipolar transistor of npn type is described.
As starting material a low doped p type monocrystalline silicone substrate
1
of (100) orientation, shown in
FIG. 1
, is used. A heavily doped bottom diffusion layer of n type, or a buried collector layer
2
, which may be made of, for example, an ion implanted layer of arsenic or antimony, is created, whereafter an epitaxic silicon layer
3
of n type is applied with a thickness of approximately 1-2 &mgr;m.
At least two variations as to where the so called trench module may be integrated in the process flow are known from the literature. According to a first variation, described by, for example the mentioned P. C. Hunt et al. and U.S. Pat. No. 4,983,226, the trench processing is performed before the definition (with LOCOS technique) of the field areas. According to the second variation, disclosed in, among other documents, EP 0, 724, 291 A2, the trench is created after the definition of the field areas. Both variations aim at the same final result, and in the following, only the first variation will be described.
A layer
4
, approximately 1 &mgr;m thick, of LPCVD (Low Pressure Chemical Vapor Deposition) oxide, which will function as a hard mask, is then deposited over the plate. Trench openings
5
a
are then defined in a lithographic way, whereafter the oxide layer
4
is etched back to reveal the underlying silicon surface. Then all photo resist is removed from the structure, whereafter the epitaxial layer
3
, the bottom diffusion layer
2
and the silicon substrate
1
are etched back using an anisotropic dry etching until a trench
5
of a predetermined depth, approximately 5-10 &mgr;m has been created (see FIG.
1
).
As the substrate is made up of lightly doped p type material, usually a small dose of low energy boron is implanted in the bottom of the trench
5
to achieve a channel stop
6
, see FIG.
2
. The channel stop
6
reduces the current amplification of the parasite transistor (n+ bottom diffusion layer/p− substrate
+ bottom diffusion layer) which is created and which increases the threshold voltage for the corresponding parasite MOS transistor. If, on the other hand, an epi-material of p−/p+ type is used as a starting material, no such implant is needed.
After the etching of the trench and the implantation of ions the hard mask
4
is removed, whereafter the semiconductor structure is oxidised thermally until a silicon oxide
7
approximately 100 nm is obtained. Then a thin silicon nitride layer
8
is deposited over the semiconductor structure, especially in the trench
5
, whereafter the trench is filled with polysilicon
9
. Alternatively an insulating or semi-insulating substance, for example silicon oxide may be used, as described in U.S. Pat. No. 4,139,442 or the above mentioned R. D. Rung et al. The filling material, which in Hunt's article is made up of polysilicon, is etched back with dry etching until the silicon nitride layer
8
is uncovered outside the trench opening
5
a.
After the filling substance
9
has been etched back, the silicon nitride layer
8
is masked and etched, whereafter silicon is oxidized by means of conventional LOCOS technique for creating both thick field oxide areas
10
and a cap oxide
11
over the trench opening, see FIG.
3
. If the trench
5
is already filled with oxide from the beginning, of course no additional cap oxidation is needed.
A collector pin
12
, connecting the bottom diffusion layer
2
to the silicon surface, is obtained, whereafter remaining areas of the silicon nitride layer
8
and the silicon oxide layer
7
are removed.
FIG. 3
shows the structure resulting from this. As an alternative, the collector pin
12
can be implanted before the trench processing, as described in U.S. Pat. No. 4,958,213.
The above described techniques have a number of drawbacks, which have led to a low yield being noticed when using trench isolation, see for example F. Yang et al. “Characterization of collector-emitter leakage in self-aligned double-poly bipolar junction transistors”, J. Electrochem. Soc., vol. 140, no. 10, 1993, p. 3033.
The commonly accepted explanation of the low yield when trench isolation is used is that the trench process (trench etching, sidewall oxidation, filling, re-etching and cap oxidation) introduces defects in the silicon substrate. A relatively detailed description of the problems of trench isolation and suggestions on how to avoid them have been the subject of a number of patents, see for example U.S. Pat. No. 4,983,226, EP 0, 278, 159 A2 and the above mentioned U.S. Pat No. 4,958,213.
Also, the descriptions are not consistent, in the sense that in U.S. Pat. No. 4,958,213 expresses the opinion that a thickness of the sidewall oxide in the trench of approximately 100 nm functions satisfactorily, whereas in U.S. Pat. No. 4,983,226 an upper limit of 45 nm is recommended for the thickness of the oxide layer. Otherwise, according to U.S. Pat. No. 4,983,226, unnecessary mechanical stress, and thereby dislocations, will be created.
In EP 0, 278 159 A2 it is described how a thin layer of polysilicon is deposited on the inside of the trench, which is later converted, in thermal oxidation, to oxide on the inside of the trench. In this way, unnecessarily heavy oxidation is avoided, and the mechanical tension or stress

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