Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-04-12
2001-09-18
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S208000, C257S207000, C257S203000, C257S367000, C257S173000, C257S174000, C257S175000, C257S355000, C257S356000, C257S357000, C257S378000, C257S773000, C257S786000
Reexamination Certificate
active
06291879
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor integrid circuit chips, and more particularly to power supply arrangement for integrated circuit chips
2. Description of the Related Art
Integrated-circuit technology currently uses multiple power and ground conductors for integrated circuits and various peripheral circuits in order to increase their operating performance and reliability. This arrangement requires that the layout plan must accommodate such conductors without increasing chip size. One solution is to provide a number of equipotential pads and provide as many power-line conductors within the interior of a chip as there are necessary for each of these pads.
Since there is a need for protecting sensitive circuit elements of an integrated circuit chip from electrostatic charges, protecting elements (or voltage sensitive devices) are located at strategic points of power-line conductors to allow “charge packets” to escape through discharge paths. However, overvoltage tests seem to indicate that part of integrated circuits still suffers from high potential charges.
SUMMARY OF THE INVENTION
The present invention is based on the discovery that current layout design for overvoltage protection is not adequate for protecting whole circuits from certain discharge patterns.
It is therefore an object of the present invention to provide a semiconductor integrated circuit chip that protects all circuit elements of the chip from all possible discharge patterns.
Another object of the present invention is to provide an integrated circuit chip in which the usually wasted corner areas of the chip are utilized.
According to one aspect of the present invention, there is provided a semiconductor integrated circuit chip comprising a plurality of equipotential power-line conductors to which circuit elements are connected, a plurality of pads connected to the power-line conductors, and a plurality of protecting elements for interconnecting the power-line conductors for protecting the circuit elements. The arrangement is such that the contact positions of the protecting elements on the conductors are nearer to respective end portions of the conductors than contact position of any of the circuit elements on the conductors. Each of the contact positions serves as a dividing point for dividing a high potential electrostatic charge into at least two low potential charges.
According to a second aspect, the present invention provides a semiconductor integrated circuit chip comprising a plurality of equipotential power-line conductors to which circuit elements are connected, a first plurality of protecting elements for interconnecting the power-line conductors for protecting the circuit elements, a plurality of input/output pads, and a second plurality of protecting elements for connecting the input/output pads to the power-line conductors. The arrangement is such that the contact positions of any of the first plurality of protecting elements and any of the second plurality of protecting elements on the conductors are nearer to respective end portions of the conductors than contact position of any of the circuit elements on the conductors. Each of the contact positions serves as a dividing point for dividing a high potential electrostatic charge into at least two low potential charges.
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patent: 5223823 (1993-06-01), Pisanto et al.
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patent: 5849355 (1998-12-01), McHenry
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Japanese Office Action dated Mar. 14, 2000 with partial translation.
McGinn & Gibb PLLC
NEC Corporation
Williams Alexander O.
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