Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means
Reexamination Certificate
1999-07-30
2001-06-26
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular chip input/output means
C257S208000, C257S723000
Reexamination Certificate
active
06252264
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to integrated circuit chips, and in particular, to chips designed for multi-chip systems, especially to aspects of packaging, layout and inter-chip communication aspects of such chips.
BACKGROUND INFORMATION
Operating speeds of integrated circuits, e.g., “IC chips”, are ever increasing. Furthermore, according to another trend, chips with extremely dense circuitry and input and output (“i/o”) traffic are being implemented on one chip and are being packaged as high-speed, multi-chip systems. High-speed processor chips are an example of this trend. These developments lead to a need to transmit signals between chips at high speeds.
There is a potential to improve communication and operating speeds by locating chips, and especially their i/o leads, close to one another. However, the layout of these very dense chips and their i/o leads is a very complicated matter, making it difficult to design features in their layout which permit such chips to be packaged close to one another.
As a result, there is a need in the art for improvements in chip and package layout, as well as inter-chip communication methods, in order to address the foregoing needs.
SUMMARY OF THE INVENTION
The present invention addresses at least some of the forgoing needs in an integrated circuit chip with a first i/o set associated with a first edge of the chip and a second i/o set associated with a second edge of the chip. The first i/o set has a physical symmetry with respect to the second i/o set, to facilitate a number of the chips being interconnected to one another on a chip carrier, with the chips symetrically disposed on the carrier.
In a further aspect, the bus, which is disposed on the chip and couples coupling the first and second i/o sets, has a turn, to facilitate straight wiring for interconnecting instances of the chip on the carrier.
In other aspects, the chip has a bus interconnecting the first and second i/o sets for transmitting signals across the chip. The bus has regeneration circuitry for regenerating said signals traversing the chip.
Further, the symmetry of the first i/o set with respect to the second i/o set is a reflection symmetry. The axis of the reflection symmetry is a diagonal between two corners of the chip. The second edge is a side adjacent to the first edge. The adjacent first and second edges have a common endpoint at a corner of the chip. One of the two corners is the common endpoint corner.
REFERENCES:
patent: 5257166 (1993-10-01), Marui et al.
patent: 5451814 (1995-09-01), Yoshimizu
patent: 6078514 (2000-06-01), Takemae et al.
Microprocessor Report: n13, v9, Oct. 2, 1995 p16 (3, ISSN0899-9341, What's Next For Microprocessing Deisign? Some Variant of Multiprocessor Seems Likely. (Industry Trend Or Event) Copyright 1995, MicroDesign Resocurces Inc.
Bailey Roger Ned
McCredie Bradley
Nealon Michael Gerard
Stigdon Hugh Rodney
Chaudhuri Olik
England Anthony V.S.
International Business Machines - Corporation
McBurney Mark E.
Pham Hoai
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