Integrated circuit chip with built-in self-test for logic fault

Details Integrated circuit chip with built-in self-test for logic fault Integrated circuit chip with built-in self-test for logic fault

1992-02-21

1993-08-24

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

371 225, 371 27, G01R 3128

Patent

active

052392627

ABSTRACT:
An integrated circuit chip with built-in self-test for logic fault detection is described which comprises a number of combinational logic circuits and a number of shift register latches. The combinational logic circuits are coupled via the shift register latches and the shift register latches are connected to form test scan paths. Test weights are created and combined with test patterns and are then applied to the test scan paths of the integrated circuit chip. In contrast to the prior art where the test weights are taken out of a weight storage table, the invention generates the test weights with the help of a so-called "finite state machine", i.e. with a circuit which creates a finite number of test weights without storing them. Therefore, no weight storage table or the like is necessary and the whole tester can be incorporated on the chip.

REFERENCES:
patent: 3719885 (1973-03-01), Carpenter et al.
patent: 4718065 (1988-01-01), Boyle et al.
patent: 4852096 (1989-07-01), Brinkman
patent: 5043988 (1991-08-01), Brglez et al.
"Test Generation Using an Efficient Weight Generator", by IBM, IBM Tech. Disc. Bull, vol. 32, #4B, Sep. 1989, pp. 429-433.
"Weighted Random Pattern Generation for Self-Test" IBM TDB, vol. 32, No. 10A, Mar. 1990, pp. 140-143.
"Design for Testability and Diagnosis in a VLSI CMOS System/370 Processor", Starke, pp. 355-362, IBM J. Res. Develop. vol. 34, No. 2/3, Mar./May 1990.
"Low-Cost LTesting of High-Density Logic Components" Bassett et al, IEEE, Apr. 1990, pp. 15-28.
"A New Procedure for Weighted Random Built-in Self-Test" Muradali et al, IEEE, Sep. 1990, pp. 660-669.
"Hardware-Based Weighted Random Pattern Generation for Boundary Scan" Brglez et al, IEEE Aug. 1989, pp. 264-274.

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