Integrated circuit chip wiring arrangement providing reduced cir

Details Integrated circuit chip wiring arrangement providing reduced cir Integrated circuit chip wiring arrangement providing reduced cir

1983-09-09

1986-04-15

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 45, 357 40, 307303, 333246, H01L 2348

Patent

active

045831114

ABSTRACT:
The area circumscribed by the current path on an integrated circuit chip is diminished, to thereby reduce the inductance of the chip and the likelihood of inductively generated errors, by disposing the bonding pads, through which the current source and current sink are respectively connected to logic gates, physically adjacent to one another. A further reduction in the area of the current loop is obtained by locating power and ground busses adjacent to one another relative to the logic gates. These two busses can be superposed one over the other on different metallic layers of the chip, so that the space between them is only the thickness of the isolation layer which separates the two metallic layers. The distribution of voltage to the logic gates is made uniform by varying the widths of the busses along their lengths in accordance with the currents they carry, and by ensuring that the total length of the current path for the gates is the same for every gate.

REFERENCES:
patent: 3365707 (1968-01-01), Mayhew
patent: 3808475 (1974-04-01), Buelow
patent: 4021838 (1977-05-01), Warwick
patent: 4255672 (1981-03-01), Ohno et al.
patent: 4475119 (1984-10-01), Kuo et al.
patent: 4499484 (1985-02-01), Tanizawa
patent: 4511914 (1985-04-01), Remedi
Journal of Digital Systems, vol. 6, No. 1, 1982, Maryland, US; Syed et al, "Single Layer Routing of Power and Ground Networks in Integrated Circuits", pp. 53-63.

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