Integrated circuit chip package with test points

Details Integrated circuit chip package with test points Integrated circuit chip package with test points

2001-01-19

2002-08-20

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S048000, C257S693000

Reexamination Certificate

active

06437436

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to flip-chips, and particularly to a package for flip-chips and a method of making and testing the same.
2. Description of the Related Art
In recent years, new technologies which can provide high-density connections to and between integrated circuits within electronic equipment have emerged. These technologies include the assembling of multichip modules which may contain several unpackaged integrated circuit (IC) chips mounted on a single substrate.
Various techniques for assembling unpackaged IC chips in a multichip module are available. These modules may be assembled by, for example, using either wire bonded connections, tape-automatic-bonded (TAB) connections, or solder flip-chip bonding, depending on the desired number and spacing of signal input-output (I/O) connections on both the chip and the substrate as well as permissible cost.
In a comparison of these three techniques, wire bonding is the most common chip-bonding technique. This technique has traditionally provided the maximum number of chip connections with the lowest cost per connection. A disadvantage of wire bonding is that inductance present in the wires used in connecting the chip to the substrate degrades the electrical performance of the circuitry in the multichip module. Also, since the I/O connections are perimeter connections on the chip and since the wires connect to the substrate on an area not occupied by the chips, wire bonding requires more area on the substrate than that required in flip-chip bonding. Finally, wire bonding requires each connection between the chip and the substrate to be made one at a time and, therefore, is time consuming and therefore expensive to assemble.
TAB bonding permits higher density I/O connections over wire bonding. This technique, however, is more expensive than wire bonding. This is, in part, because TAB bonding requires special tooling for each different chip design. Also like wire bonding, TAB bonding similarly requires I/O perimeter connections and therefore more area on a substrate than flip-chip bonding. There is also undesirable parasitic inductance which imposes a penalty on electrical performance of the IC chip circuitry connected using this bonding technique.
Flip-chip bonding of a multichip module is achieved by providing an IC chip with either perimeter or area array solder-wettable metal pads which comprise the signal (I/O) terminals on the chip, and a matching footprint of solder-wettable pads on the substrate. Before assembly onto the substrate, either the chip, the substrate, or both typically undergo a processing step wherein a solid solder bump is deposited at each signal (I/O) terminal on an IC chip or on both an IC chip and a substrate. The chip is then turned upside down, or flipped, and placed in an aligned manner on top of a substrate such that the solder bumps align with the wettable metal pads, or such that a pair of solder bumps on the chip and the substrate align with each other. All connections are then made simultaneously by heating the solder bumps to a reflow temperature at which the solder flows and an electrically conductive joint between the contact pads on both the substrate and the IC chip is formed. Such a process is described by R. R. Tummala and E. J. Rymaszewski in
Microelectronics Packaging Handbook
, New York: Van Nostrand Reinhold, 1989, pp. 366-391.
Thus flip-chip bonding of IC chips used in multichip modules provides the advantage of requiring less area on a substrate and thereby facilitates high-density interconnections of the chips comprising the module. Since the interconnections are short, well controlled electrical characteristics are provided. High-speed signals are thus propagated in and through the module with minimum delay and distortion. Also since flip-chip bonding is a batch process, all interconnections are made quickly and simultaneously through a solder reflow step.
It is usually necessary to test IC units after manufacture; however, the high density of IC mounting enabled by flip-chip technology compounds the complexity of testing. There is a need to provide a simplified means for testing IC units fabricated by flip-chip methods, particularly for ensuring that the solder reflow has occurred uniformly over an entire unit.
SUMMARY OF THE INVENTION
The present invention provides a substrate and a plurality of stiffener walls, each stiffener wall carrying an IC, wherein the stiffener walls and ICs are fixed to the substrate with electrical continuity being established between the substrate and the stiffener walls and IC's through conductive bumps (solder bumps or conductive epoxy bumps). The substrate and the stiffener walls include test points on their surfaces, and also include printed wiring connecting at least the test points and the conductive bumps. Some of the printed wiring is arranged to establish paths between test points. Some of the paths between test points pass through portions of ICs. The test paths facilitate testing of conductivity through the conductive bumps, and functional testing of the ICs.
Thus, the invention provides simple and inexpensive means of testing dense and complex IC packages, including verification that the solder reflow process has been effected uniformly throughout the entire package.
Other objects and features of the present invention will become apparent from the following detailed description considered in conjunction with the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.


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