Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
2007-11-19
2010-11-30
Silver, David (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S003000, C703S014000, C703S018000
Reexamination Certificate
active
07844435
ABSTRACT:
An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs:A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates;B) In core pair-wise frequency Dependent RL extraction;C) In core equivalent circuit synthesis;D) caching and partitioning RL extraction techniques for run time efficiency; andE) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.
REFERENCES:
patent: 5629860 (1997-05-01), Jones et al.
patent: 5761076 (1998-06-01), Miki
patent: 5894220 (1999-04-01), Wellstood et al.
patent: 6061508 (2000-05-01), Mehrotra et al.
patent: 6086238 (2000-07-01), Mehrotra et al.
patent: 6317859 (2001-11-01), Papadopoulou
patent: 6342823 (2002-01-01), Dansky et al.
patent: 6418401 (2002-07-01), Dansky et al.
patent: 6865727 (2005-03-01), Frerichs et al.
patent: 2002/0144224 (2002-10-01), Frerichs et al.
patent: 2007/0225925 (2007-09-01), Suaya et al.
patent: 2007/0226659 (2007-09-01), Suaya et al.
A. Dansky, H. Smith, P. Williams, “On-Chip Coupled Noise Analysis of a High Performance S/390 Microprocessor”, Electronic Components and Technology Conference, pp. 817-825, May 1997.
A. Deutsch, et al, “When are Transmission-Line effects Important for On-Chip Interconnections?”, IEEE Transactions on Microwave Theory and Techniques, vol. 45, pp. 547-567, Oct. 1997.
A. Deutsch, H. H. Smith, G. V. Kopcsay, B. L. Krauter, C. W. Surovic, P. W. Coteus, “Multi-Line Crosstalk and Common-Mode Noise Analysis”, Proc. Dig. IEEE 9th Topical Meeting on Electrical Performance of Electronic Packaging, Scottsdale, AZ, Oct. 23-25, 2000.
A. Deutsch, H. H. Smith, C. W. Surovic, G. V. Kopcsay, D. A. Webber, P. W. Coteus, G. A. Katopis, W. D. Becker, A. H. Dansky, G. Sai-Halasz, P. J. Restle, “Frequency-Dependent Crosstalk Simulation for On-Chip Interconnections”, IEEE Trans. Advanced Packaging, vol. 22, No. 3, pp. 292-308, Aug. 1999.
B. Averill,et al, “Chip Integration Methodology for the G5/G6 Custom Microprocessors”, IBM JRD, vol. 43, No. 5/6, pp. 681-706, 1999.
W. T. Weeks, L. L. Wu, M. F. McAllister, A. Singh, “Resistive and Inductive Skin Effect in Rectangular Conductors”, IBM J. Res. Develop., vol. 23, pp. 652-660, 1979.
Gerard V. Kopcsay. “Avoiding Non-Physical Elements in RL Impedance Representations”, unpublished report, Mar. 2001.
Bowen Michael A.
Deutsch Alina
Kopcsay Gerard V.
Krauter Byron L.
Rubin Barry J.
International Business Machines - Corporation
Kinnaman, Jr. William A.
Silver David
LandOfFree
Integrated circuit chip having on-chip signal integrity and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit chip having on-chip signal integrity and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit chip having on-chip signal integrity and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4226591