Integrated circuit chip device having balanced thermal...

Details Integrated circuit chip device having balanced thermal... Integrated circuit chip device having balanced thermal...

1998-04-28

2001-01-23

Graybill, David E. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S738000, C257S748000

Reexamination Certificate

active

06177728

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to electronic packaging and more particularly to methods and apparatus for improving the reliability of flip-chip connections by balancing differences in thermal expansion of the chip and the substrate to which it is attached.
BACKGROUND
Integrated circuit (IC) chips or modules are often connected to chip carriers, and sometimes directly to PC boards or cards, by what is commonly referred to as C4 (controlled-collapsed-chip-connection) or flip-chip attachment technology. Small bumps, drops or balls of solder are formed on an active surface of the chip. The chip is then turned over (hence the name “flip-chip”) and placed on the carrier, board or other substrate to which it will be attached. The components are heated to cause the solder to reflow in a controlled collapse which completes electrical connections between the chip and substrate. This technology has numerous advantages, including compact connections, electrical performance and cost, that have made it one of the industry standards. There are certain disadvantages, however, that have prevented even wider adoption.
One of the more significant disadvantages results from differences in the coefficients of thermal expansion (CTE) of the chip and substrate. Common chip materials such as silicon, germanium and gallium arsenide usually have CTEs of about 3 to 6 ppm/° C. Circuitized organic chip carriers to which the chips are attached, which are usually composites of organic dielectrics and metallic circuitry, tend to have CTEs between about 15 and about 25 ppm/° C. So do the circuitized organic printed circuit boards and cards to which the carriers are normally attached, and to which chips are sometimes attached directly. As these components are heated and cooled the carriers, boards or cards expand and contract much more than the chips. With a simple chip to substrate connection, the strain from the unequal expansion and contraction is absorbed primarily by the soft solder. With repetitive thermal cycles, which are inescapable with many electronic components, the solder joints are likely to fail.
A conventional approach to this problem is to surround the solder joints with a dielectric underfill material that matches or approximates the CTE of the solder joints, typically about 22 to about 30 ppm/° C. Commonly used underfill materials include Dexter Hysol FP4511, Ablestik Ablebond 7717 and Polyset PCX-16-10A. They are normally heavily filled with very small particles of materials such as silicon dioxide to produce the desired CTE. The filler also gives the underfill a high Young's modulus, typically greater than 2GPa or 2.9×10
5
psi. The underfill absorbs most of the strain resulting from the differential expansion of the chip and substrate, which protects the solder joints. However, by restricting the expansion of the substrate, the relatively stiff underfill has a tendency to warp the carrier, board or other substrate to which the chip is attached. When a carrier is attached to a printed circuit board or card, warping the carrier generates tensile forces in the ball grid array between the carrier and the board or card which reduce the reliability of the ball grid array.
There have been many attempts to mitigate these problems, including stiffeners with a desirable CTE and layers of material such as Copper-Invar-Copper (CIC) within a multi-layer organic substrate. Stiffeners are expensive, however, and CIC has several inherent problems, not the last of which is the difficulty in drilling through it for Z axis conductors or vias. Thus, the need for reliable and inexpensive ways to compensate for differential thermal expansion between chips and circuitized organic substrate such as chip carriers and printed circuit boards remains.
SUMMARY OF THE INVENTION
The packages and methods of this invention compensate for CTE differentials between chips and the organic dielectric carriers, boards or other substrates to which the chips are attached with a layer of a thermoplastic material that modifies the CTE of at least one component of the package and thereby reduces CTE differentials. As may be seen in the accompanying drawings and the following Detailed Description, the thermoplastic material may be applied to the entire surface of a chip carrier, printed circuit or other substrate, or form an interior layer of a multi-layered structure. It may also be applied to selected regions or areas on the surface of a carrier or other substrate where adjustment is required. For example, a localized application may be preferable for carriers that hold a number of chips.
The thermoplastic material is preferably a thermotropic polymer, i.e., a polymer whose physical properties can be altered by extrusion or other physical processes. Liquid crystalline polyesters are especially preferred because these polyesters have an ordered morphology, and excellent mechanical properties can be achieved through processing variations. As will be seen below, coefficients of thermal expansion can be varied over a wide range to suit objectives of this invention. These materials are thermally conductive, have good dielectric properties and adhesive strength, and can be readily drilled to form plated through holes or PTHs. Since they are thermoplastic, they are reworkable and do not release significant quantities of volatile materials.


REFERENCES:
patent: 4658332 (1987-04-01), Baker et al.
patent: 4740414 (1988-04-01), Shaheen
patent: 4847146 (1989-07-01), Yeh et al.
patent: 4873615 (1989-10-01), Grabbe
patent: 5026624 (1991-06-01), Day et al.
patent: 5049981 (1991-09-01), Dahringer
patent: 5258648 (1993-11-01), Lin
patent: 5262280 (1993-11-01), Knudsen et al.
patent: 5278010 (1994-01-01), Day et al.
patent: 5304457 (1994-04-01), Day et al.
patent: 5347162 (1994-09-01), Pasch
patent: 5371404 (1994-12-01), Juskey et al.
patent: 5439766 (1995-08-01), Day et al.
patent: 5439779 (1995-08-01), Day et al.
patent: 5473119 (1995-12-01), Rosenmayer et al.
patent: 5473814 (1995-12-01), White
patent: 5493075 (1996-02-01), Chong et al.
patent: 5496769 (1996-03-01), Marion et al.
patent: 5511306 (1996-04-01), Denton et al.
patent: 5535101 (1996-07-01), Miles et al.
patent: 5579573 (1996-12-01), Baker et al.
patent: 5633535 (1997-05-01), Chao et al.
IBM Technical Disclosure Bulletin, pp. 85-86, vol. 40 No. 04, Apr. 1997.
09/067,708; filed Apr. 28, 1998; inventor Jimarez et al. for Methods and Apparatus for Balancing Differences in Thermal Expansion in Electric Packaging.
09/080,117; field May 15, 1998; inventor Caletka et al.. for Thermally Enhanced and Mechanically Balanced Flip Chip Package and Method of Forming.

Affiliated with

Also associated with

Rating

Integrated circuit chip device having balanced thermal... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit chip device having balanced thermal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit chip device having balanced thermal... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2540745