Integrated circuit cell placement using optimization-driven clus

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364489, 364491, G06F 1750

Patent

active

055660789

ABSTRACT:
An integrated circuit layout technique is described which employs an optimization-driven clustering technique to provide improved cell placement. The technique utilizes clustering of cells based upon Rent's rule, with global-optimization-derived inter-cell distances being used to break ties when identical Rent exponents are encountered. A constraint on the number of cells permitted to be in a cluster and a constraint on the maximum Rent exponent which to be considered for merging clusters minimize the "overgrowth" of clusters and serve to even out cluster size, ideally suiting the technique to conventional partitioning and placement schemes.

REFERENCES:
patent: 4495559 (1985-01-01), Gelatt, J. et al.
patent: 4500963 (1985-02-01), Smith et al.
patent: 4554625 (1985-11-01), Otten
patent: 4593363 (1986-06-01), Burstein et al.
patent: 4612618 (1986-09-01), Pryor et al.
patent: 4630219 (1986-12-01), DiGiacomo et al.
patent: 4688072 (1987-08-01), Heath et al.
patent: 4890238 (1989-12-01), Klein et al.
patent: 4908772 (1990-03-01), Chi
patent: 4918614 (1990-04-01), Modarres et al.
patent: 5202840 (1993-04-01), Wong
patent: 5212653 (1993-05-01), Tanaka
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5222031 (1993-06-01), Kaida
patent: 5237514 (1993-08-01), Curtin
patent: 5267176 (1993-11-01), Antreich et al.
patent: 5311443 (1994-05-01), Crain et al.
patent: 5349536 (1994-09-01), Ashtaputre et al.
patent: 5353235 (1994-10-01), Do et al.
Ding et al., "A New Optimization Driven Clustering Algorithm for Large Circuits," Oct. 26, 1992.
"A Linear-Time Heuristic for Improving Nerwork Partitions", by Fiduccia, Manuscript, Apr. 1982, 7 pages.
"Improvements of a Mincut Partition Algorithm", by Ng et al., CH2469-5/1987, IEEE, pp. 470-473.
"Clustering Based Simulated Annealing for Standard Cell Placement", by Mallela, 25th ACM/IEEE Design Automation Conference, 1988, pp. 312-317.
"Proud: A Fast Sea-Of-Gates Placement Algorithm", by Tsa et al., 25th ACM/IEEE Design Automation Conference, 1988, pp. 318-323.
"Finding Clusters in VLSI Circuits", by Garbers et al., IEEE, 1990, pp. 520-523.
"An Efficient Placement Method for Large Standard-Cell and Sea-Of-Gates Designs", by Kappen et al., IEEE, 1990, pp. 312-316.
"Gordian: VLSI Placement by Quadratic Programming and Slicing Optimization", by Kleinhans et al., IEEE Transactions on Computer-Aided Design, vol. 10, No. 3, Mar. 1991, pp. 356-365.
"New Spectral Methods for Ration Cut Partitioning and Clustering", by Hagen et al., IEEE Transactions on Computer-Aided Design, vol. 11, No. 9, Sep. 1992, pp. 1074-1085.
"Net Partitions Yield Better Module Partitions", by Cong et al., 29th ACM/IEEE Design Automation Conference, 1992, pp. 47-52.
"Gordian: A New Global Optimization/Rectangle Dissection Method for Cell Placement", by Kleinhans et al., pp. 506-509.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Integrated circuit cell placement using optimization-driven clus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit cell placement using optimization-driven clus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit cell placement using optimization-driven clus will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1251935

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.