Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including contaminant removal or mitigation
Patent
1999-01-28
2000-06-13
Bowers, Charles
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including contaminant removal or mitigation
438108, 438906, 257778, 134 13, H01L 2144, H01L 2148, H01L 2150, H01L 2348, H01L 2352, H01L 2940
Patent
active
060748974
ABSTRACT:
A technique for enabling sufficient flow of flux cleaning fluids and an underfill material in the relatively low-profile gap between a flip-chip bonded IC chip and a substrate, such as a printed circuit board, is to provide at least one aperture in the substrate under the IC chip. The use of such an aperture enables, for example, flux cleaning fluid to flow through the aperture into the low-profile gap between the IC chip and the substrate surface, such as by the application of pressure or by gravity, which then exits through openings between formed interconnect bonds at a sufficient flow rate to adequately remove flux residues. An epoxy underfill to the IC chip can be formed in a similar manner. For example, a relatively thick bead of epoxy, such as on the order of the thickness of the IC chip, is deposited or stencil printed on the substrate surface around the edges of the IC chip and capillary action is then relied upon to draw the epoxy into the low-profile gap. Undesirable air pockets which otherwise would develop form the displaced air as the epoxy flows into the low-profile gap can advantageously escape through the aperture of the invention.
REFERENCES:
patent: 4320047 (1982-03-01), Murphy
patent: 5211764 (1993-05-01), Degani
patent: 5385290 (1995-01-01), Degani
patent: 5477611 (1995-12-01), Sweis
patent: 5534078 (1996-07-01), Breunsbach
patent: 5656862 (1997-08-01), Papathomas
patent: 5710071 (1998-01-01), Beddingfield
patent: 5794330 (1998-08-01), Distefano
patent: 5855821 (1999-01-01), Chau
R. R. Tummula, et al., Microelectronics Packaging Handbook pp. 366-391 (Van Nostrand Reinhold, New York, NY, 1989).
Degani Yinon
Greenberg Lawrence Arnold
Berezny Nema
Bowers Charles
Lucent Technologies - Inc.
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