Integrated circuit arrangement with layer stack

Details Integrated circuit arrangement with layer stack Integrated circuit arrangement with layer stack

2011-06-14

2011-06-14

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S734000, C257S750000, C257S753000, C257S758000, C257SE23001, C257SE23142, C257SE23157, C257SE23163, C257S768000

Reexamination Certificate

active

07960832

ABSTRACT:
An integrated circuit arrangement includes an electrically conductive conduction structure made from copper or a copper alloy. At a side wall of the conduction structure, there is a layer stack which includes at least three layers. Despite very thin layers in the layer stack, it is possible to achieve a high barrier action against copper diffusion combined with a high electrical conductivity, as is required for electrolytic deposition of copper using external current.

REFERENCES:
patent: 5003428 (1991-03-01), Shepherd
patent: 5942799 (1999-08-01), Danek et al.
patent: 6500761 (2002-12-01), Wajda et al.
patent: 6508919 (2003-01-01), Licata et al.
patent: 6586794 (2003-07-01), Nakamura et al.
patent: 6624516 (2003-09-01), Fujisawa et al.
patent: 6724087 (2004-04-01), Buynoski et al.
patent: 2002/0048937 (2002-04-01), Selsley
patent: 2003/0197205 (2003-10-01), Marsh et al.
patent: 2004/0051117 (2004-03-01), Chyan et al.
patent: 2004/0155348 (2004-08-01), Lee
patent: 2006/0027925 (2006-02-01), Huang et al.
patent: 2007/0252187 (2007-11-01), List et al.
patent: 2008/0157072 (2008-07-01), Zaidi
patent: 2010/0245306 (2010-09-01), Koyama et al.
patent: 2001-044073 (2001-02-01), None
patent: 2001-291844 (2001-10-01), None
patent: 2002-34859 (2002-11-01), None
patent: 2003-203878 (2003-07-01), None
patent: 2003-524888 (2003-08-01), None
patent: 2004-031866 (2004-01-01), None
patent: 2004-518291 (2004-06-01), None
patent: WO 01/29893 (2001-04-01), None
patent: WO 02/059944 (2002-08-01), None
patent: WO 2004/042815 (2004-05-01), None
Japanese Office Action, with English translation, dated Apr. 27, 2010 (8 pages).
Japanese Office Action, with English translation, dated Aug. 17, 2010 (6p).

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