Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-10-15
2003-07-22
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S374000, C257S659000, C257S630000, C257S500000, C257S294000, C257S275000, C257S340000, C257S228000, C257S244000, C438S348000, C438S361000, C438S272000, C438S152000, C361S800000, C361S824000, C333S246000, C333S247000
Reexamination Certificate
active
06597053
ABSTRACT:
In modern circuit designs, in order to increase packing density and shorten connection paths, power semiconductors are integrated on one chip together with their control logic. Examples of this are found in motor controls or in ABS circuits and airbag drives in the automotive field. It is necessary here to protect the sensitive drive logic from the interference of strong disturbing influences from the power semiconductor.
Previously, the drive logic of the power semiconductors was separated galvanically (cf. A. Nakagawa et al., ISPS 1990, p. 97 to 101). To this end, the modules were integrated on silicon wafers comprising a thin SiO
2
layer beneath the active Si region. The galvanic separation was obtained by etching trenches around the circuits, said trenches extending to the insulating SiO
2
layer.
The thus obtained shielding of the drive logic against interference is inadequate against high-frequency disturbing impulses, however. Rapid switching processes can trigger an uncontrolled responding of the logic.
U.S. Pat. No. 5,306,942 teaches an integrated circuit arrangement with at least one structural element that is delegated in a first substrate, which element is shielded by a shielding structure from electrical fluctuations of the first substrate caused by another structural element of the circuit arrangement. To this end, a shielding structure is created which surrounds a bottom half of the structural element laterally and comprises a bottom horizontal shielding element. To generate such an integrated circuit arrangement, a method is described in which an annular depression is created in a surface of a substrate. An insulating layer and a layer of polysilicon are subsequently deposited. A thick layer of SiO
2
is deposited on this and planarized. On the planarized surface of the SiO
2
layer, a second substrate is deposited as a carrier. The rear side of the first substrate is then ground thin, until the insulating layer is exposed. Parts of the conductive layer serve as a shielding structure. In a part of the first substrate that is surrounded by the shielding structure, source/drain regions are created by implantation. A gate electrode and contacts are created over these. Since high temperatures are required in order to deposit the carrier and to create the source/drain regions, doped polysilicon, which has a high melting point, is used for the shielding structure.
Japanese Patent Application No. 61/290 753 demonstrates an integrated circuit arrangement in which a lateral metallic structure is arranged next to a structural element. To this end, depressions which are lined with an insulating layer and filled with conductive material are arranged in a surface of a substrate at which the structural element adjoins.
European Patent Application No. 0 567 694 describes an integrated circuit arrangement with at least two blocks, which are separated from one another by an insulating layer. A metallic plate is arranged between them, in order to limit the capacitive coupling between the first and second blocks.
U.S. Pat. No. 5,122,856 describes a circuit arrangement which is integrated in a substrate, which arrangement can switch electrical signals from a surface of the substrate to a rear side of the substrate. To this end, depressions are made in the rear side of the substrate, which are lined with an insulating layer. A contact element extends along a sidewall of the depression. Stacks comprising structural elements can be arranged on top of each other in that electrodes of the structural elements are connected to one another by heating.
U.S. Pat. No. 5,266,511 describes a three-dimensional integrated circuit arrangement in which substrates comprising structural elements are stacked on top of one another. The structural elements are arranged in monocrystalline layers. The connecting of the substrates is accomplished by heating two adjacent SiO
2
layers of the substrates to approximately 900° C. Structural elements that are stacked on top of one other are electrically connected to one another other by contacts
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an integrated circuit arrangement in which structural elements are shielded against interference, even high-frequency disturbing impulses, and a method for the production thereof.
This object is inventively achieved in accordance with the invention by a metallic shielding structure that acts as a Faraday cage, which structure surrounds the structural element to be protected, and in a method for the production therof.
The term “structural element” is used here for individual elements such as diodes and transistors as well as for circuit structures comprising a number of elements.
Protecting structural elements with a metallic shielding structure brings the advantage of avoiding the high costs associated with the use of the above described wafers containing SiO
2
.
By the metallic shielding structure, the structural elements are protected from interfering impulses not only of neighboring power semiconductors, but of any origin. The necessity for an additional shielding against interfering impulses from the environment is forgone. This keeps the volume of the chip particularly small.
The structural elements can be integrated into a three-dimensional circuit arrangement. Substrates comprising structural elements are thus joined on top of each other in a stacked fashion. Compared to the common two-dimensional arrangement, which is conditional to the use of a common substrate material for all modules, the three-dimensional arrangement increases the combinatorial possibilities with regard to the material and production process of the various structural elements. Sensor elements or high-speed GaAs-Hf transistors can thus be combined with silicon CMOS logic, for example.
To produce one part of the shielding structure, the surfaces of the structural elements are provided with a metallic layer, and their electrical contacts are subsequently electrically insulated from the metallic layer by etching away the metallic layer around the contacts. It is advantageous to use two different metals for the metallic layers of two structural elements that are arranged adjacently in the stack, the alloy of which has a melting point above the melting point of at least one metal. If the structural elements are now brought together, and their metallic layers are heated to a temperature below the melting point of the alloy, at which one metal is solid and the other liquid, then the metals mix, which results in a hardening, due to the higher melting point of the alloy. The metals of the shielding structure thereby simultaneously serve to permanently connect two adjacent structural elements in the stack.
It is advantageous to use tin as one metal, since it has a low melting point. Copper can be chosen as the other metal.
It is advantageous to deposit an auxiliary layer made of Ti or TiN prior to applying the metals onto the surface, which layer improves the adhesion of the metallic layer and forms a barrier against diffusion of the metals into metallic parts of the surface of the structural elements.
It is advantageous to apply an additional auxiliary layer of copper prior to the application of the tin, in order to improve the adhesion further.
These and other features of the invention(s) will become clearer with reference to the following detailed description of the presently preferred embodiments and accompanied drawings.
FIG. 1
is a cross-section through a first substrate, in whose top layer there is a structural element with a top and a bottom contact, and with an electrical connection, this being surrounded by a first lateral shielding element in the top layer, which is interrupted for purposes of leading the electrical connection through.
FIG. 2
is a cross-section through the first substrate of
FIG. 1
, on whose top surface an auxiliary layer and a top horizontal shielding element is deposited.
FIG. 3
is a cross-section through a second substrate, in whose top layer there is a structural element with a top and a
Anthofer Anton
Hübner Holger
Mitchell James
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
Talbott David L.
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