Integrated circuit arrangement having at least two mutually insu

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

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Details

257513, 257515, 257396, 257397, H01L 2900, H01L 2976

Patent

active

059905360

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

Trench insulation is used in semiconductor technology, especially MOS technology, in order to isolate components in a substrate electrically from one another given a small width of an insulation region. A longitudinal trench which is completely filled with SiO.sub.2 is mainly used as trench insulation. The depth of the trench generally corresponds approximately to the smallest structure dimension in the respective technology.
Leakage currents in the bulk are prevented by the trench insulation. If insulating layers and conductive layers are arranged on the surface of the trench, then leakage currents may occur at the surface on account of parasitic MOS components. These leakage currents must also be prevented by the trench insulation.
In order to improve the insulation behaviour of the trench insulation, doped regions which prevent the formation of conductive channels are employed in the region of the trench insulation. These doped regions are generally produced by implantation. However, this implantation influences the parameters of the components which are insulated from one another.
It has furthermore been proposed to enlarge the cross-section of the trench in the region of the bottom section of the trench. The components to be insulated are arranged on the surface of the substrate (see German Reference DE 38 09 218 A1).


SUMMARY OF THE INVENTION

The invention is based on the problem, therefore, of specifying an integrated circuit arrangement in which at least two components are insulated from one another in a space-saving manner and any impairment of the properties of the components due to implantation which is necessary for the insulation is avoided. It is furthermore intended to specify a method for the production of such an integrated circuit arrangement.
The integrated circuit arrangement according to the invention is integrated in a semiconductor substrate. The semiconductor substrate preferably comprises monocrystalline silicon or the monocrystalline silicon layer of an SOI substrate.
Arranged in the semiconductor substrate is a trench, which reaches from a main area of the semiconductor substrate down into the semiconductor substrate. At least one side of the trench is provided with an insulation structure which insulates a first component from a second component. That side of the trench which is provided with the insulation structure has a bulge, with the result that the width of the trench is greater in the region of the trench bottom than in the region of the
The first component is arranged on the main area and the second component is arranged on the trench bottom. The insulation structure covers the side arranged between the two components. The increased thickness of the insulation structure in the region of the bulge ensures that a parasitic MOS component which may possibly be produced along the side has such a high threshold voltage that at the operating voltages no leakage currents occur at the surface of the side.
The insulation structure reaches from the main area right down to the trench bottom. The thickness of the insulation structure, that is to say the extent of the insulation structure perpendicular to the side, is in this case greater in the region of the bulge than at the main area. The lateral extent of the insulation structure according to the invention is greater in the substrate than at the main area of the substrate. As a result, the insulation effect of the insulation structure is improved compared with the value which would be obtained with an insulation structure which has the constant lateral extent at the main area over the entire depth.
Since the insulation structure is arranged on the side of the trench, the first component and the second component can be arranged directly next to one another when projected onto the main area. Since the first component is arranged on the main area and the second component is arranged on the trench bottom and the insulation structure is arranged between them on the trench side, they are insulated from one

REFERENCES:
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patent: 4894695 (1990-01-01), Ishii et al.
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patent: 5176789 (1993-01-01), Yamazaki et al.
patent: 5229318 (1993-07-01), Strboni et al.
patent: 5336912 (1994-08-01), Ohtsuki
patent: 5512517 (1996-04-01), Bryant
Patent Abstracts of Japan, E-649, Aug. 25, 1988, vol. 12 No. 314, Hitachi, Ltd., and Katsutada Horiuchi, Semiconductor Device, JP 63-78573 dated Apr. 8, 1988.
Journal of the Electrochemical Society, Solid-State Science and Technology, Aug. 1987, M. Engelhardt et al, A New CbrF.sub.3 Process for Etching Tapered Trenches in Silicon, pp. 1985-1988.
Academic Press, Inc., (1984) VLSI Electronics Microstructure Science, vol. 8, Plasma Processing for VLSI, edited by Norman G. Einspruch et al, pp. 124-127.

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