Integrated circuit arrangement

Details Integrated circuit arrangement Integrated circuit arrangement

1985-12-11

1988-04-26

Atkinson, Charles E.

Excavating

371 25, G01R 3128, G06F 1100

Patent

active

047409703

ABSTRACT:
A circuit arrangement for use in an integrated circuit having a built-in self test design, the circuit arrangement comprising first and second gates coupled to a flip-flop via a third gate. The present invention provides a multiplexer coupled to one input of the first gate, the multiplexer being controllable by a control signal to feed either input data or output data of the circuit arrangement to said one input of the first gate and a fourth gate coupled to an input of the second gate, the fourth gate having an input connected to receive a signal dependent on the control signal to the data selector means.

REFERENCES:
patent: 4320509 (1982-03-01), Davidson
patent: 4340857 (1982-07-01), Fasang
patent: 4433413 (1984-02-01), Fasang
patent: 4493078 (1985-01-01), Daniels
patent: 4594711 (1986-06-01), Thatte
patent: 4597080 (1986-06-01), Thatte et al.
Konemann et al., Built-In Test for Complex Digital Integrated Circuits, IEEE Journal of Solid-State Circuits, vol. 3C-15, No. 3, Jun. 1980, pp. 315-319.
Fasang, Circuit Module Implements Practical Self-Testing, Electronics, May 19, 1982, pp. 164-167.
LeBlanc, LOCST: A Built-In Self-Test Technique, IEEE Design & Test, Nov. 1984, pp. 45-52.

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