Excavating
Patent
1997-08-19
1999-04-13
Chung, Phung M.
Excavating
371 221, G01R 3128, G06F 1100
Patent
active
058944834
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to an integrated circuit arrangement; more specifically, it relates to a circuit arrangement that is equipped with edge-oriented terminals or pins, or similar means of connection, hereafter called connecting isles or bond pads.
Integrated circuit arrangements of this kind are adapted to process, in a controlled manner, the structure of incoming signals that appears at bond pads or at input pads in internal function blocks, in order to generate a signal pattern at bond pads for outgoing signals or at output pads.
The invention is based on the potential for using a circuit arrangement that belongs to the integrated circuit, and is adapted so that it may be used to test the internal function blocks of the integrated circuit by verifying that a selected signal structure at the input pads results in a determined signal pattern at the output pads when a function works correctly. If there is a lack of agreement, the testing equipment used generates an error-indicating signal.
The present invention is specifically adapted to be used with relatively large integrated circuit arrangements that may be divided into other, large or small, "discrete" physical and/or logical function blocks.
The input node and the output node that belong to each function block, or group of function blocks, that is to be tested must be available to the input and output pads that belong to the integrated circuit arrangement.
Further, the present invention is intended to present an integrated circuit arrangement in which a predetermined number of bond pads, divided into input and output pads, belong to test cells that are meant to make available a digital signal structure, that is adapted to provide a test of the integrated circuit as described above.
It may be specifically pertinent to use test cells that are based on the principles of Boundary-Scan architecture, specifically standardized Boundary-Scan architecture.
It should be noticed that standardized Boundary-Scan cells (BS-cells) have a first active circuit configuration for the input pads (BS-input cells), a second active circuit configuration for output pads (BS-output-cells), and a third active circuit configuration for I/O-pads, with a bond pad for incoming or outgoing signal direction. There is also a fourth standardized BS-cell for activating signals at tri-state outputs and for I/O-pad cells. However, this BS-cell has no specific function relative to the conditions of the present invention, and therefore is not mentioned hereafter.
Only BS-input cells for input pads, or BS-output cells for output pads, will be shown in the description that follows and in the Claims, since the circuit configuration for BS-cells, such as an I/O-pad, can easily be used solely as a BS-input cell for input pads or as a BS-output cell for output pads.
According to the present invention, it is true that the pictured circuit arrangement is primarily based on the Boundary-Scan application. However, any modification required to apply the inventive thought to another circuit arrangement, using any kind of test cell at the input pads, output pads, and/or I/O-pads, is obvious for a person skilled in the art.
Thus, the present invention is based on the knowledge that to perform an adequate test of integrated circuits and the function blocks that belong to them, specifically structured testing vectors must be used; for example, to apply a signal structure of logical values, `1`s and `0`s, to selected input pads.
These tests are necessary since, when integrated circuits are produced, it is not uncommon for one of the nodes in the circuit to stuck at `1` or `0`. Obviously, these errors must be discovered.
The testing vectors are designed according to an algorithm whose purpose is to discover every node, within a given integrated circuit, that is stuck at `1` or `0`.
The present invention is generally based on the condition that the integrated circuit can be equipped with test cells that are related to the input and output pads.
The test cells for the input pads must
REFERENCES:
patent: 5260949 (1993-11-01), Hashizume et al.
patent: 5281864 (1994-01-01), Hahn et al.
Chung Phung M.
Telefonaktiebolaget LM Ericsson
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