Integrated circuit architecture formed of parametric macro-cells

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307303, 364488, 437 51, G06F 1560, H03K 326

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047018607

ABSTRACT:
An integrated circuit architecture methodology effectively comprises the use of high level building blocks (termed macro-cells) that are composed of a customized arrangement of a number of smaller but readily chip-layout repeatable building blocks termed micro-cells. The size of each macro-cell is determined by signal processing design/performance/operational parameters of the system. The internal configuration geometry and signal port connections of each microcell are customized for circuit packaging density, performance and interconnectability with other micro-cells.

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Szepieniec et al; "The Genealogical Approach to the Layout Problem"; Automation Confer. (ACM) 1980; pp. 535-542.
Koide et al; "Building Block Approach & Variable Size Memory for CMOS VLSIs"; IEEE Int.Solid-State Ckts Conf. 1983; pp. 148-149.
Sugiyama et al; "Data Processing System of E-B Litho. for VLSI Microfabrication"; IEEE Trans Electron Dev. Apr. 1979 (vol. ED-26 No. 4); pp. 675-685.

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