Integrated circuit annealing methods and apparatus

Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing

Reexamination Certificate

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C700S108000, C219S121600, C219S121850

Reexamination Certificate

active

06675057

ABSTRACT:

TECHNICAL FIELD
The subject matter relates generally to the field of semiconductors and, more particularly, to improved methods and apparatus for thermal annealing of integrated circuits.
BACKGROUND INFORMATION
During the fabrication of integrated circuits (ICs), IC's typically undergo a heat treating or thermal annealing process following implantation or doping of the wafer, prior to segmentation of the wafer into individual dice. Annealing helps to repair the silicon lattice structure following doping, and it also functions to activate the dopant. Annealing is generally performed within a temperature range of 600-1400 degrees Centigrade.
In the field of semiconductor electronics there is an incessant competitive pressure among manufacturers to improve the quality of their products while driving down production costs. This is particularly true regarding the annealing of ICs. ICs must be annealed in a carefully controlled manner that sufficiently heats them without overheating them. Furthermore, the annealing process should preferably be performed quickly and in an energy-efficient manner.
It is known to employ a rapid thermal annealing (RTA) process that raises the temperature of the entire silicon wafer for a few seconds using, for example, heat lamps radiating the doped wafer surface while providing cooling to the wafer back side. However, the RTA process can be difficult to control, because the lamp turn-on times are variable, as are the back side cooling rates.
It is also known to employ pulsed or stepped laser annealing, in which a pulsed laser beam is directed sequentially at each die. The laser beam is turned on very briefly, e.g. for 20 nanoseconds (ns), and it is then turned off while the beam is stepped to the next die. However, laser annealing at 20 ns engenders a significant problem, because the thermal diffusion length in this time scale in silicon is approximately only 0.5 microns, which is comparable to the feature size on a deep sub-micron IC chip. Thus the temperature in the active area is very different from the temperature in the field area. This generally causes the polysilicon traces in the field area to melt and disintegrate during laser annealing. Although the use of a protective film lessens this problem somewhat, such films increase production costs and can cause additional problems.
Thus the RTA process is too slow and unpredictable, and pulsed laser annealing is too fast and heats too little of the wafer. An ideal process should have a process time in the range of 1 microsecond to 1 millisecond, and it should have a thermal diffusion length of 5-100 microns.
It is known to use a pulsed laser having a longer pulse width, but this approach has two problems. First, the laser energy stability is poor, being normally worse than 3%. Secondly, the annealing throughput is low, because the laser has to step through each die on the silicon wafer.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for a thermal annealing process that provides effective annealing at a relatively high throughput rate.


REFERENCES:
patent: 3900737 (1975-08-01), Collier et al.
patent: 4131487 (1978-12-01), Pearce et al.
patent: 4316074 (1982-02-01), Daly
patent: 4415794 (1983-11-01), Delfino et al.

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