Integrated circuit and process for identifying minimum or...

Details Integrated circuit and process for identifying minimum or... Integrated circuit and process for identifying minimum or...

2006-07-04

2006-07-04

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07072922

ABSTRACT:
Apparatus and process identifies a maximum or minimum value among a plurality of binary values on a plurality of a-bit wide wires in an integrated circuit module. An N-bit vector K is calculated based on n most significant bits of all a-bit binary signals, where N=2n. M N-bit vectors K—0, . . . ,K_(M−1) are calculated based on the n most significant and the m least significant bits of all a-bit binary signals, where M is at least 2m−1. A table is constructed from vectors K—0, . . . ,K(M−1) to create table vectors. A table vector is selected based on vector K, is used to derive a vector P, which in turn is used to select another table vector. The minimum or maximum binary value is identified from the two selected table vectors.

REFERENCES:
patent: 4998219 (1991-03-01), Frauenglass
patent: 5721809 (1998-02-01), Park
patent: 6931424 (2005-08-01), Joseph
Timing-Driven Logic Bi-Decomposition', Jun. 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 22, iss.6, pp. 675-685—Author(s)—Cortadella.

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