Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1998-12-18
2002-06-18
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S528000, C257S003000, C257S004000
Reexamination Certificate
active
06407441
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to improved integrated circuit devices and more articularly to an improved integrated circuit which provides low-loss and low-crosstalk passive component integration and is suitable for Radio Frequency Integrated Circuits (RFICs) applications.
BACKGROUND OF THE INVENTION
The background is described in connection with an improved substrate suitable for RFIC applications. It should be understood, however, that the principles disclosed may apply to a wider array of applications where substrate-related losses are a concern.
Inductors are essential elements of Radio Frequency (RF) circuits. They are needed for inter-stage impedance matching, filtering, and decoupling of AC/DC signals. Impedance matching plays a critical role in RF circuit design. For example, low noise amplifiers using MOSFETs normally need inductively tuned inputs to lower the input impedance and improve the receiver noise figure. Inductors are commonly used in both the input and output of RF power amplifiers to improve the power gain and power added efficiency. Impedance matching would be more effective if inductors were brought closer to the active devices, motivating development of on-chip matching for RF integrated circuits.
Several forms of inductors are used with RF circuits. Air coil inductors are commonly used at operating frequencies of less that 1 GHz. Although air coil inductors are simple to design and fabricate, their three-dimensional structure makes them unsuitable for integration on either semiconductor chips or fiber-glass circuit boards. Moreover, air coil inductors must be assembled in conjunction with other packaged components on a circuit board.
Transmission line inductors become practical in size above 10 GHz. Their simple structure makes them readily integratable on glass fiber circuit boards or semiconductor substrates if the latter also have high resistivity greater than 1000 ohm-cm.
Cellular phones and wireless LANs operating in the 1 to 6 GHz range have created new challenges for inductor design. Neither aircoil nor transmission line inductors are suitable for cellular phone applications because of their large size. Spiral inductors have now become a focus for technology development due to their small size and their two-dimensional design which is compatible to 1 to 6 GHz on-chip integration.
At the same time, the advance of submicron CMOS has prompted the use of BICMOS and CMOS for RFIC design. In such applications, however, low substrate resistivity which played an insignificant role in digital circuits presents major problems for RFIC designers. For example, spiral inductors integrated directly on the BICMOS or CMOS substrates normally showed low Q because the inductors must absorb substantial substrate losses.
As a result various silicon substrate technologies have been examined to solve this problem. Table 1 below lists the prior art silicon substrate technologies which have been explored to date.
TABLE 1
Prior Art Substrate Technologies
Technique
Sources
Comments
High-R Silicon
Westinghouse
Unconventional IC Substrates
Motorola
Glass refill
M-COM
Limited to passive components
Silicon on sapphire
Peregrine
Not mainstream processes
Polyimide coating
Hughes
Require > 10 &mgr;m thick polyimide
Samsung
Air isolation
UCLA
Not compatible to IC processes
Multi-level metal
IBM, National
Does not address substrate loss
TI
Among these silicon substrate technologies, other than the IBM multi-level metal inductor approach, none of them can be adopted for main line silicon wafer fab facility. Furthermore, the IBM approach addresses the inductor metal loss but not the substrate loss, making it unsuitable for RFIC designs.
Porous Silicon is well known to those of skill in the art as a material with high resistivity and performance characteristics close to GaAs. The development of porous silicon, however, has been largely limited to silicon light emitting diodes. It was also tried for device isolation in which the porous silicon was used as an intermediate process step to create buried oxide layers.
Porous silicon is formed by anodization of silicon producing an interconnected sub-100 Å pore structure within a single crystal silicon matrix. The process is quite rapid. For example, a 100 &mgr;m layer can be formed within 15 minutes on wafers of any diameter. Masks can be used to limit the formation of porous silicon to selected areas of the wafer. It is even possible to grow relatively high quality epitaxial silicon over porous silicon. Prior art processes for the development and formation of porous silicon are plentiful and include: I. J. Beale, et al., “An experimental and Theoretical Study of the Formation and Microstructure of Porous Silicon,” J. Crystal Growth 73 (1985) 622-636; A. G. Nassiopoulos, et al., “Sub-Micrometer Luminescent Porous Silicon Structures Using Lithographically Patterned Substrates.” Thin Solid Films, vol. 255 (1995), 329; M. Lee. et al., “Utilization of GaAs Masking Layers for Formation of Patterned Porous Silicon,” Jpn. J. Appl. Phys., vol. 35 (1996), 3116.
Silicon RFICs in either monolithic integration forms or silicon-on-silicon multichip modules have been developed to improve the footprint, cost, and performance of a cellular phone design. Their application to cellular phones were hampered, until the present invention, by RF isolation passive component integration problems and RF/DC grounding problems. Other developments have shown that high-Q inductors can be fabricated on greater than 1000 ohm-cm silicon substrates. In the meantime, power amplifiers using less than 0.01 ohm-cm p+ substrate grounded design have showed good performance in the 1-2 GHz range. The invention provides a method to create both high resistivity and low resistivity materials on the same silicon wafer, thus solving the RF isolation and RF/DC grounding problems that has hampered RFIC development.
SUMMARY OF THE INVENTION
The invention provides the reduction of silicon substrate losses by the insertion of a thick (100 &mgr;m) high resistivity (>1000 ohm-cm) porous silicon layer between passive components such as inductors and the bulk silicon wafer. Porous silicon exhibits high resistivity greater than 1000 ohm-cm and, as such, its use is ideal when integrated with low resistivity silicon for good isolation of passive RF components. A low resistivity silicon motherboard using locally defined porous silicon can provide a via free DC/RF grounding platform eliminating some of the high costs processes associated with prior art motherboard designs. An advantage of using porous silicon in the substrate is increased RFIC performance approaching that of GaAs integrated circuits.
Another advantage is that due to its thick high resistivity layer, the porous silicon motherboard of the present invention permits the integration of all passive RF components on a single chip.
Still another advantage is increased production yield as the silicon IC components can be assembled on the motherboard directly without the concerns of thermal expansion differences.
Disclosed in one embodiment is an improved integrated circuit platform with low-loss and low-crosstalk characteristics which permits the integration of RF passive components such as inductors, capacitors and resistors. Selective regions of porous silicon are created on a layer of silicon substrate. Later, AC/DC terminals can be added to the substrate to create a fully functional platform. Compared to prior art fiber glass or ceramic circuit boards, the integrated circuit platform of the present invention is smaller in size and low in manufacturing costs since it shares the same silicon wafer fabrication facility.
In another embodiment, a porous silicon layer of created over a silicon substrate for formation of an RF CMOS chip where a thick layer of locally placed porous silicon is formed after all active CMOS devices are fabricated. This enables low temperature fabrication of RF isolated passive components in a conventional CMOS fabrication line.
Other aspects and advantages of the inve
Fenty Jesse A.
Gamer Jacqueline J.
Lee Eddie
LandOfFree
Integrated circuit and method of using porous silicon to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit and method of using porous silicon to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit and method of using porous silicon to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2960490