Patent
1980-10-01
1983-03-29
Edlow, Martin H.
357 41, 357 49, 357 51, H01L 2978
Patent
active
043785654
ABSTRACT:
An integrated circuit structure for reducing propagation delay is described. Integrated circuits include at least a pair of regions in each of which are located a respective plurality of functional cells and which are spaced apart by an interconnection region in which interconnection lines are provided connecting elements of the functional cells of one functional cell region with elements of the functional cells of the other functional cell region. Field oxide is provided in the interconnection region substantially greater in thickness than the field oxide in the regions of the functional cells thereby substantially reducing the capacitance and hence propagation delay of the interconnection lines. Formation of the field oxide of the interconnection region independent of the formation of the field oxide in the functional cell regions enables optimization of the field oxide in the interconnection region for minimum propagation delay without compromising functional cell formation in the functional cell regions.
REFERENCES:
patent: 4131906 (1978-12-01), Kinoshita
patent: 4317273 (1982-03-01), Guterman
Ghezzo Mario
Jerdonek Ronald T.
Davis Jr. James C.
Edlow Martin H.
General Electric Company
Snyder Marvin
Zaskalicky Julius J.
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