Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-12-05
2004-08-24
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000, C257S700000, C257S723000, C257S782000
Reexamination Certificate
active
06781239
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits and, more particularly, to an integrated circuit and method of forming the integrated circuit that has a die with high Q inductors and capacitors that is formed on a die with a circuit as a flip chip.
2. Description of the Related Art
Low-loss, linear inductors and capacitors are common circuit elements in radio frequency (RF) applications, such as digital cellular telephones. These devices tend to be quite large with respect to the digital circuitry, and are one of the limiting factors in further significant reductions in the size of digital cellular telephones.
For example, one important measure of an inductor is the quality factor or Q of the inductor. High Q inductors are desirable in a number of RF circuits, such as resonant circuits. The Q of an inductor is given by equation (EQ.) 1 as:
Q=&ohgr;L/R,
EQ.1
where &ohgr; is related to the frequency f of the signal applied to the inductor (&ohgr;=2(&pgr;)(f)), L represents the inductance of the inductor, and R represents the resistance of the inductor.
As indicated by EQ. 1, the smaller the resistance, the higher the Q of the inductor. One common approach to reducing the resistance of an inductor is to increase the size of the inductor. In addition, capacitors, like inductors, have a similar Q measure which increases with increasing size. As a result, high Q inductors and capacitors are often implemented at the circuit board level as discrete components, requiring a significant amount of circuit board space.
One approach to providing an integrated circuit with high Q inductors and capacitors is to fabricate both the electrical circuit and the high Q inductors and capacitors on the same semiconductor substrate. This approach, however, typically suffers from a number of drawbacks, including induced substrate currents and relatively thick metal layers.
Another approach to providing an integrated circuit with high Q inductors and capacitors that address these drawbacks is the use of micro-electromechanical systems (MEMS) technology. For example, using MEMS technology, the functionality of a low loss inductor and capacitor can be provided by using micron-sized electromechanical structures.
Although techniques exist for providing an integrated circuit with high Q inductors and capacitors, there is a continuing need for alternate structures and methods of forming the structures.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit with a die that is attached to another die as a flip chip. The flip chip die has micro-electromechanical structures that realize high Q inductors and/or capacitors, while the other die has an electrical circuit that utilizes the high Q inductors and/or capacitors. The use of two dice in the integrated circuit simplifies the manufacturing process and increases manufacturing flexibility.
An integrated circuit in accordance with the present invention includes a first die that has a substrate with an electrical circuit, and an interconnect that is formed on the substrate and electrically connected to the electrical circuit. The first die also has a passivation layer that is formed on the interconnect, and a plurality of first bonding pads that are formed on the passivation layer. The first bonding pads are electrically connected to the interconnect. The first die further has a plurality of second bonding pads that are formed on the passivation layer. The second bonding pads are electrically connected to the interconnect.
The integrated circuit also includes a second die that has a micro-electromechanical structure which has an inductance, and a plurality of third bonding pads that are connected to the micro-electromechanical structure. The integrated circuit further includes a plurality of connectors that are attached and electrically connected to the second bonding pads and the third bonding pads.
The present invention also includes a method of forming the integrated circuit. The method includes the step of forming a first die from a first wafer. The first die has a substrate with an electrical circuit, and an interconnect that is formed on the substrate and electrically connected to the electrical circuit. The first die also has a passivation layer that is formed on the interconnect, and a plurality of first bonding pads that are formed on the passivation layer. The first bonding pads are electrically connected to the interconnect. The first die further has a plurality of second bonding pads that are formed on the passivation layer. The second bonding pads are electrically connected to the interconnect.
The method further includes the step of forming a second die from a second wafer. The second die has a micro-electromechanical structure which has an inductance, and a plurality of third bonding pads that are connected to the micro-electromechanical structure. In addition, the method includes the step of attaching the third bonding pads of the second die to the second bonding pads of the first die via a plurality of connectors.
In further accordance with the method of the present invention, the first die is fabricated at a first facility using a first sequence of fabrication steps, while the second die is fabricated using a different second sequence of fabrication steps at either the first facility or a second facility. Further, the third bonding pads of the second die can be attached to the second bonding pads of the first die at the first facility, the second facility, or a third facility.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.
REFERENCES:
patent: 6399416 (2002-06-01), Wark
Harper, Electronic Packaging and Interconnection Handbook, 1991, McGraw Hill, 6.71-73.*
Wolf et al., Silicon Processing for the VLSI Era, 2000, Lattice Press, vol. 2, 826-829.
Padmanabhan Gobi R.
Yegnashankaran Visvamohan
Andujar Leonardo
Flynn Nathan J.
National Semiconductor Corporation
Pickering Mark C.
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