Integrated circuit and method of arbitration in a network on...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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Reexamination Certificate

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08005097

ABSTRACT:
The invention relates to an integrated circuit and to a method of arbitration in a network on an integrated circuit. According to the invention, a method of arbitration in a network on an integrated circuit is provided, the network comprising a router unit, the router unit comprising a first input port, a second input port and an output port, wherein the router unit receives at least one first packet via the first input port, and wherein the router unit receives at least one second packet via the second input port, the router unit arbitrating between the first packet and the second packet, characterized in that the step of arbitrating is performed using a first label and a second label, the first label being attached to the first packet, and the second label being attached to the second packet. This method relies on the perception that the arbitration performed by a router should be based on connection arbitration instead of input port arbitration. This means that instead of merely arbitrating between the contending input ports in a router, the arbitration should also take into account the connections to which packets correspond. This can be done by attaching labels to the packets, which labels are used in the arbitration process. In this way, it is possible to achieve a fair allocation of bandwidth to different connections, regardless of on which input ports these connections are established.

REFERENCES:
patent: 6751698 (2004-06-01), Deneroff
patent: 2002/0027914 (2002-03-01), Shinohara
patent: 2002/0085552 (2002-07-01), Tandon
patent: 2002/0105965 (2002-08-01), Dravida
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patent: 1130855 (2001-09-01), None
patent: 1130855 (2002-09-01), None
patent: WO0072533 (2000-11-01), None
patent: WO2004051942 (2004-06-01), None
“A Router Architecture for Networks on Silicon”—Proceedings of Progress 2001 2nd Workshop on Embedded Systems to Rijpkema et al.
“Scheduling Algorithms for Input-Queued Cell Switches”—Ph.D. thesis, University of California at Berkeley, 1995, by N. McKe.
Written Opinion of the International Searching Authority for International Application No. PCT/IB2006/051526.

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