Integrated circuit and method including an isolation...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C257S510000, C257SE21546

Reexamination Certificate

active

08003490

ABSTRACT:
An integrated circuit and method including an isolation arrangement. One embodiment provides a substrate having trenches and mesa regions and also auxiliary structures on the mesa regions. A first isolation structure covers side walls and a bottom region of the trenches and at least partially side walls of the auxiliary structure. A liner on the first isolation structure fills the trenches and gaps between the auxiliary structures with a second isolation structure; and the second isolation structure is pulled back, wherein upper sections of the liner are uncovered.

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patent: 2009/0068817 (2009-03-01), Eun

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