Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2011-07-12
2011-07-12
Pham, Chi H (Department: 2471)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C713S320000
Reexamination Certificate
active
07978693
ABSTRACT:
An integrated circuit having a plurality of processing modules (M, S) and an interconnect means (N) for coupling said plurality of processing modules (M, S) and for enabling a packet based communication based on transactions between said plurality of processing modules (M, S) is provided. Each packet comprises a first predetermined number of subsequent words each having a second predetermined number of bits. A first of said plurality of processing modules (M) issues a transaction by sending at least one packet over said interconnect means (N) to a second of said plurality of processing modules (S). The integrated circuit further comprises at least one packet inspecting unit (PIU) for inspecting bits of said at least one packet to determine bits not required for said issued transaction and for matching said not required bits of said at least one inspected packet with other bits of the same packet.
REFERENCES:
patent: 5572736 (1996-11-01), Curran
patent: 5790874 (1998-08-01), Takano et al.
patent: 5856980 (1999-01-01), Doyle
patent: 6535984 (2003-03-01), Hurd
patent: 6725450 (2004-04-01), Takayama
patent: 7020821 (2006-03-01), Chang
patent: 2002/0186597 (2002-12-01), Henkel et al.
patent: 2003/0212914 (2003-11-01), Webster et al.
patent: 2004/0202190 (2004-10-01), Ricciulli
patent: 2005/0010830 (2005-01-01), Webster
patent: 02095574 (2002-11-01), None
patent: WO 02095574 (2002-11-01), None
Interface Exploration for reduced power in Core-Based systems, Tony Givargis, 1998 IEEE, pp. 117-122.
Givargis Tony, interface Exploration for Reduced Power in Core-Based Systems, 1998 IEEE, pp. 117-122.
E. Rijpkema et al, “Trade Offs in the Design of a Router With Both Guaranteed and Best-Effort Services for Networks on Chip”, Design, Automation and Test in Europe Conference NAD Exhibition, Mar. 3-7, 2003, Munich, German.
T.T. Ye et al, “Packetized On-Chip Interconnect Communication Analysis for MPSoC”, Design Automation and Test in Europe, Proceedings, 2003, pp. 344-349.
J. Dielissen et al, “Concepts and Implemetation of the Philips Network-On-Chip”, Internet Article, Nov. 2003, XP002330547, p. 1-6.
E. Rijpkema et al, “A Router Architecture for Networks on Silicon”, Proceedings of Process 2001, 2nd Workshop on Embedded Systems.
Koninklijke Philips Electronics , N.V.
Mohebbi Kouroush
Pham Chi H
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