Integrated circuit and method for operating the integrated...

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S201000, C327S407000

Reexamination Certificate

active

06847581

ABSTRACT:
An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.

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patent: 6400188 (2002-06-01), Baket et al.
patent: 6452849 (2002-09-01), Iwamoto
patent: 197 30 806 (1999-01-01), None
patent: 0 785 624 (1997-07-01), None

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