Integrated circuit and method for fabrication thereof

Details Integrated circuit and method for fabrication thereof Integrated circuit and method for fabrication thereof

1974-09-03

1980-04-22

Larkins, William D.

357 15, 357 44, 357 48, 357 89, 357 92, H01L 2710

Patent

active

041997751

ABSTRACT:
An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the collector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.

REFERENCES:
patent: 3736477 (1973-05-01), Berger et al.
patent: 3775192 (1973-11-01), Beale
patent: 3823353 (1974-07-01), Berger et al.
patent: 3869622 (1975-03-01), Shimizu
Schuenemann et al., IBM Tech. Discl. Bulletin, vol. 15, No. 2, Jul. 1972, pp. 509-510.
Berger, "Bipolar Devices for Low Power Digital Applications . . .", Solid State Devices 1973, (The Institute of Physics, London) (Proc. 3rd European Solid State Device Research Conference, Munich, Sep. 18-21, 1973), pp. 118-123.

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