Integrated circuit and method for biasing an epitaxial layer

Details Integrated circuit and method for biasing an epitaxial layer Integrated circuit and method for biasing an epitaxial layer

1984-04-02

1986-03-18

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 35, 357 48, 357 51, 307303, 307299R, 307296R, H01L 2972, H03K 326

Patent

active

045772118

ABSTRACT:
An integrated circuit and method for biasing an impurity region, in particular an epitaxial layer, to a level substantially equal to a supply voltage level yet exhibiting a high reverse breakdown voltage to negative transients of the supply voltage. The integrated circuit and method is of especial utility in power BIMOS and other applications having the substrate at or near the supply voltage level.

REFERENCES:
patent: 3829709 (1974-08-01), Maigret et al.
Davis, W. F., "Bipolar . . . Environment", IEEE Journal of Solid-State Circuits, vol. Sc-8, No. 6, Dec., 1973, pp. 419-427.

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