Metal treatment – Compositions – Heat treating
Patent
1980-07-09
1982-12-07
Roy, Upendra
Metal treatment
Compositions
Heat treating
29576B, 29577C, 148187, 357 34, 357 43, 357 91, H01L 754, H01L 2978
Patent
active
043625746
ABSTRACT:
A method used to form a field effect device and a bipolar device in different regions of the same semiconductor material, such method including the step of forming a doped layer in the semiconductor material which extends from the surface of the semiconductor material to a predetermined depth in such semiconductor material and which extends laterally along the surface of the semiconductor material through the different regions wherein the field effect device and the bipolar device are formed. Such formed doped layer has the same type conductivity as that of the semiconductor material but has a doping concentration at least an order of magnitude greater than that of the semiconductor material. The doping concentration of the doped layer is sufficiently high to prevent undesired surface state inversion effects and enable effective control of the channel width of the field effect device. On the other hand, the doping concentration of the doped layer is sufficiently low to provide proper breakdown voltages for both the bipolar device and the field effect device. In this way, since the same doping concentration is used for both the bipolar device region and the field effect device region, the doped layer may be formed in the entire surface region of the semiconductor material without the requirement of additional masking steps. Further, with a buried channel field effect device the portion of the doped layer in the field effect device region provides the upper comparatively higher doped gate portion of the device while the portion of the semiconductor material below the buried channel region provides the lower gate portion of the device, such upper and lower gate portions being coupled to a gate electrode to enable control of the effective channel width from both upper and lower sides thereof.
REFERENCES:
patent: 4066917 (1978-01-01), Compton
patent: 4074301 (1978-02-01), Palvinen
patent: 4108686 (1978-08-01), Jacobus, Jr.
patent: 4113513 (1978-09-01), DeBrebisson
patent: 4120707 (1978-10-01), Beasom
patent: 4140547 (1979-02-01), Shibata et al.
patent: 4143392 (1979-03-01), Mylroie
patent: 4212683 (1980-07-01), Jones et al.
patent: 4218267 (1980-08-01), Maddox, Jr.
patent: 4233615 (1980-11-01), Takemoto et al.
patent: 4276095 (1981-06-01), Beilstein, Jr.
Pippenger et al. Electronics Design, I (Jan. 1978) p. 104.
Pannone Joseph D.
Raytheon Company
Roy Upendra
Sharkansky Richard M.
LandOfFree
Integrated circuit and manufacturing method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit and manufacturing method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit and manufacturing method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1901645