Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2000-07-31
2002-01-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S114000
Reexamination Certificate
active
06338974
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit analytical techniques and, in particular, to integrated circuit analytical imaging techniques.
2. Description of the Related Art
Integrated circuit (IC) analytical imaging techniques (e.g., photon emission microscopy techniques and voltage contrast analysis techniques) are commonly employed during failure analysis of semiconductor device structures. In such techniques, radiation (e.g., visible and/or near infra-red [IR] wavelength photons) emitted from an IC during the application of a test signal is collected and analyzed to form an image, from which information can be derived about the operation and/or failure mode of the IC. Further descriptions of IC analytical imaging techniques are available in E. I. Cole and D. L. Barton,
Failure Site Isolation: Photon Emission Microscopy Optical/Electron Beam Techniques
, in Failure Analysis of Integrated Circuits: Tools and Techniques, 87-112 (Kluwer Academic Publishing 1999) and Ching-Lang Chiang, et al.,
Backside Emission Microscopy for Integrated Circuits on Heavily Doped Substrate
, Proceedings from the 24th International Symposium for Testing and Failure Analysis (15-19 November, 1998), both of which are hereby fully incorporated by reference.
FIG. 1
depicts, in cross-section, a conventional semiconductor device structure
10
. Semiconductor device structure
10
includes a semiconductor substrate
12
(typically, 400 microns or more in thickness) with an IC (not shown) formed in and on the semiconductor substrate. The formation of an IC in and on the semiconductor substrate
12
typically entails the creation of both an active circuit layer
14
(e.g., a 10 micron thick epitaxial silicon layer) in the semiconductor substrate
12
and a metal interconnect layer
16
(e.g., a
4
micron thick metal interconnect layer) on the semiconductor substrate
12
. Such a semiconductor device structure has an upper surface
18
and a lower surface
20
.
Metal interconnect layer
16
includes opaque metal lines (not shown) that can block the emission of radiation from the upper surface
18
of the semiconductor device structure
10
. In addition, it has become increasingly common to package semiconductor device structures using flip-chip packaging techniques that require the use of opaque solder bumps on the upper surface
18
. The presence of opaque metal lines and solder bumps, however, makes it difficult to conduct IC analytical imaging techniques that involve the collection of radiation emitted from the upper surface of a semiconductor device structure. Consequently, IC analytical imaging techniques that involve the collection of radiation emitted from the lower surface (commonly referred to as “backside IC analytical imaging techniques”) of a semiconductor device structure are gaining in popularity and importance. A drawback of such backside IC analytical imaging techniques, however, is that the semiconductor substrate (e.g., a silicon substrate) attenuates the radiation being emitted from the IC. This attenuation occurs since the semiconductor substrate acts as a band-pass filter.
To minimize attenuation of emitted radiation by the semiconductor substrate, the semiconductor substrate is commonly thinned via mechanically polishing prior to the collection of emitted radiation.
FIG. 2
illustrates the semiconductor device structure
10
of
FIG. 1
after the semiconductor substrate has been thinned via mechanical polishing to form a thinned semiconductor substrate
22
. The thinned semiconductor substrate can have a thickness, for example, of 100 microns. The dashed lines indicate the boundaries of semiconductor substrate
12
prior to thinning. One effect of mechanical polishing, however, is the creation of a rough backside surface
24
that includes a plurality of peaks
26
and valleys
28
. Such a rough backside surface
24
can scatter radiation (e.g., photons) being emitted from the IC, resulting in a degraded image. The scattering of radiation by the rough backside surface
24
can be minimized if a mirror-like backside surface is created during thinning of the semiconductor substrate. Producing such a mirror-like backside surface, however, requires complex, time-consuming and expensive techniques. For example, 10 hours of mechanical polishing can be required to decrease the roughness of a backside surface from 100 angstroms (peak-to-valley) to 50 angstroms (peak-to-valley).
Still needed in the field, therefore, is an IC analytical imaging technique that eliminates the need to produce a mirror-like backside surface. In addition, the IC analytical imaging technique should be relatively simple, fast and inexpensive.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit (IC) analytical imaging process that eliminates the need to produce a mirror-like backside surface. In addition, the process is simple, fast and inexpensive. Processes in accordance with the present invention include steps of first providing a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate formed of a semiconductor material (e.g., a silicon substrate, GaAs substrate or other III-V compound substrate) and an IC. The IC is formed in and on the semiconductor substrate. Next, the semiconductor substrate is thinned by removing semiconductor material from the lower surface of the semiconductor substrate. This thinning creates a thinned semiconductor substrate that has a backside surface. The backside surface of the thinned semiconductor substrate has a roughness due to the presence of a plurality of peaks and valleys thereon. A backside surface fill material (e.g., water, optical grade oil or optical grade epoxy) is subsequently applied to the backside surface of the thinned semiconductor substrate. The application of the backside surface fill material creates a backside surface fill material layer, which at least partially fills the valleys.
After application of the backside surface fill material, an analytical imaging technique (e.g., photon emission microscopy techniques or voltage contrast analysis techniques) is performed by collecting radiation emitted through the backside surface.
Since the backside surface fill material layer at least partially fills the valleys of the backside surface, the transmissivity and efficiency of radiation emitted through the backside surface is improved due to a reduction in radiation scattering. In addition, processes in accordance with the present invention are lower in cost, simpler and less time consuming (i.e., faster) than conventional processes that create a mirror-like backside surface via mechanical polishing.
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Gary Shade et al.,Photoemission Microscopy, in Microelectronic Failure Analysis: Desk Reference, 181-196 (Thomas W. Lee et al. eds., Asm Intl. 1993).
Edward I. Cole Jr. et al.,Failure Site Isolation: Photon Emission Microscopy Optical/Electron Beam Techniques, in Failure Analysis of Integrated Circuits: Tools and Techniques, (Lawrence C. Wager eds., Kluwer Academic Publishing 1999).
Ching-Lang Chiang and Daniel T. Hurley,Dynamics of Backside Wafer Level Microprobing, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual, 137-149 (1998).
Ching-Lang Chiang, Neeraj Khurana and Daniel T. Hurley,Backside Emission Microscopy for Integrated Circuits on Heavily Doped Substrate, Proceedings from the 24th International Symposium for Testing and Failure Analysis (Nov. 15-19, 1998).
Christian Boit,Photoemission Microscopy-Advanced/Theory of Operation, 213-229.
Dang Phuc T.
National Semiconductor Corporation
Nelms David
Stallman & Pollock LLP
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