Integrated circuit analysis system and method using model...

Details Integrated circuit analysis system and method using model... Integrated circuit analysis system and method using model...

2005-12-07

2009-02-17

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S027000, C716S030000

Reexamination Certificate

active

07493247

ABSTRACT:
A method and system for verifying an integrated circuit using a Model Checker at post-silicon time to improve post-silicon assertion-based verification. A dialog is established between the Model Checker and a fabricated integrated circuit under test (ICUT), to increase the state space which is explored. ICUT-based traces from the integrated current are generated, in part based on initial states and assertions provided by the Model Checker or by a user. The Model Checker verifies the integrated circuit by generating Model Checker-based traces from basic logic, which are reproductions of the ICUT-based traces.

REFERENCES:
patent: 7137086 (2006-11-01), Abramovici
patent: 7305635 (2007-12-01), Abramovici et al.

Affiliated with

Also associated with

Rating

Integrated circuit analysis system and method using model... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit analysis system and method using model..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit analysis system and method using model... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4125750