Integrated circuit adapted for ECO and FIB debug

Details Integrated circuit adapted for ECO and FIB debug Integrated circuit adapted for ECO and FIB debug

2006-04-25

2006-04-25

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S758000

Reexamination Certificate

active

07034384

ABSTRACT:
An integrated circuit adapted for ECO and FIB debug comprises: a substrate, a spare cell, a top-layer output terminal pad and a top-layer output terminal pad. The spare cell is disposed in substrate and comprises at least one input terminal and at least one output terminal. The top-layer output terminal pad and the top-layer input terminal pad are disposed in a top metal layer. The top metal layer is disposed over the substrate. The top-layer output terminal pad and the top-layer input terminal pad are electrically coupled to the output terminal and input terminal of the spare cell by a via structure, respectively.

REFERENCES:
patent: 4609809 (1986-09-01), Yamaguchi et al.
patent: 6255845 (2001-07-01), Wong et al.

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