Integrated circuit

Details Integrated circuit Integrated circuit

2002-02-04

2003-09-02

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Parallel controlled paths

37

Reexamination Certificate

active

06614290

ABSTRACT:

FIELD OF THE INVENTION
The invention pertains to an integrated circuit comprising at least a first and a second circuit and a first and a second signal path between the first and the second circuit, the first and the second signal path each comprising a selection element having a first input coupled to the first circuit, a second input, and an output coupled to the second circuit, the second input of the selection element of the second signal path being coupled to a memory element.
BACKGROUND OF THE INVENTION
For reasons of design and test efficiency, IC-design usually runs along the lines of identifying a number of more or less independent sub-functions and implementing these sub-functions as separate circuits or functional blocks, also called cores or macros. In a later design stage, the various (analog and/or digital) macros are interconnected through a number of signal paths, thereby eventually enabling the IC to perform its intended functionality. Production testing of such an IC is preferably carried out according to the macro test concept, i.e. all macros are tested individually, rather than that the IC is tested as a whole. For further information on macro testing reference is made to U.S. Pat. No. 5,477,548.
WO 99/56396 describes a seam circuit for coupling such a first and a second circuit within an IC, the seam circuit comprising a selection element and a memory element. The selection element and the memory element form a feedback loop, in that the memory element is coupled between an output and a first input of the selection element. In order to enable scanning of the memory elements, the latter are formed by flip-flops having apart from a data input a scan data input, which is either coupled to an input of the scan chain, or to a preceding element of the scan chain. The flip flops comprise a selection input to select between the data input and the scan data input. During normal operation of the IC, the selection element is set into a first state in which it selects the signal offered at its first input. In that state the selection element, e.g. a multiplexer functionally couples the second circuit to the first circuit with only the delay of the selection element. At the same time the output signal of the selection element may be read into the memory element, so as to observe the output of the first circuit. In the second state the selection element selects the signal offered at its second input, which is provided by the memory element. This provides for the possibility of controlling the input of the second input. The memory elements formed by the flip-flops form part of a scan chain. For that purpose each flip-flop within the chain has a scandata input coupled to an output of a preceding flip-flop in the chain and an output coupled to a scandata input of the succeeding flip-flop in the chain. The scandata input of the first flip-flop of the chain forms the input of the scan chain, and the output of the last flip-flop in the chain forms the output of the scan chain. It is a drawback of the known IC that relative complex test circuitry is described therein. In order to enable the memory element to select either a first input (data) or a second input (test data), it requires an additional selection element.
SUMMARY OF THE INVENTION
It is a purpose of the invention to provide an IC which also enables production testing, but which has simpler test circuitry. The IC according to the invention, therefore is characterized in that the selection element of the second signal path has an output coupled to an input of the memory element. The test circuitry of the IC of the invention is simpler than that of the known IC, in that only one selection element is required for each signal path which has to be controlled or observed. It is however possible to apply the same test functions as is possible with the known IC. The IC according to the invention likewise has a normal operating state and a test state. In the normal operating state the selection elements are in a first state in which they functionally couple the second circuit to the first circuit via the respective signal paths. In the scan state the selection elements connect the memory elements to each other so as to form the scan chain. During normal operation the output signal of the selection elements may be read into memory elements, so as to observe the operation of the first circuit. And during the scan state the inputs of the second circuits may be controlled.
The embodiment of claim
2
has the advantage that each of the inputs of the second circuit may be controlled simultaneously. Alternatively each of the outputs of the first circuit may be controlled simultaneously. Since a latch requires less components than a flip-flop, the embodiment of claim
3
has the advantage that a still further simplification of the test circuitry is achieved. Still each of the signal paths may be observed or controlled, albeit that a first half should be tested in a first test cycle, and the second half in a second test cycle.


REFERENCES:
patent: 5309444 (1994-05-01), Dartois et al.
patent: 5675589 (1997-10-01), Yee
patent: 5960008 (1999-09-01), Osawa et al.
patent: WO9956396 (1999-11-01), None

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