Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2000-09-07
2002-11-05
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S240000, C257S272000, C257S369000, C257S371000, C257S392000
Reexamination Certificate
active
06476430
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to an integrated circuit with at least two field-effect transistors of a certain conductivity type, comprising a semiconductor body having a surface region of a first conductivity type adjoining a surface, which is provided with surface zones of the second, opposite, conductivity type forming source and drain zones of said transistors. Such a device is disclosed, for example, in patent document U.S. Pat. No. 5,547,894.
It is well-known that the trend towards ever smaller dimensions of transistors leads to unfavorable changes in certain properties, often referred to as short-channel effects. For example, in the case of a smaller channel length, i.e. a channel length in the sub-micron range, it is possible that, as a result of punch-through between source and drain, the threshold voltage becomes dependent upon the channel length L and, for example, in the case of n-channel transistors becomes lower as L becomes smaller. To suppress these punch-through effects, a halo implantation (often also referred to as pocket implantation) is customarily carried out, resulting in the formation, around the source and drain zones or at least around the LDD parts of these zones, of higher-doped zones of the first conductivity type having a higher doping concentration than the background concentration of the surface region. Provided the doping concentration of the halo zones is not excessively high, it is achieved by these zones, which extend from the source and the drain into the channel over only a very small distance, that the above-described reduction of the threshold voltage as a function of the channel length is completely, or partly, suppressed.
A drawback of the halo implantation resides in that the properties of the transistors become less favorable for analog applications, particularly as regards the output resistance which is reduced substantially. As a result, circuits for both digital and analog signal processing are difficult to design in deep sub-micron technology. It is an object of the invention to provide, inter alia, an integrated circuit which also comprises transistors with good properties for analog applications, while the advantages of the halo implantation are preserved.
SUMMARY OF THE INVENTION
An integrated circuit of the type mentioned in the opening paragraph is characterized in accordance with the invention in that only one of said transistors, hereinafter referred to as first transistor, is provided with a halo implantation to suppress short-channel effects, and in that the other transistor, hereinafter referred to as second transistor, which fulfills an analog function in the circuit, is free of said halo implantation and has a larger channel length than the first transistor. As a result of the absence of the halo implantation in the second transistor, intended for performing analog functions, the output resistance of the transistor is high, i.e. much higher than in the first transistor with halo implantation. By additionally choosing a larger channel length for the second transistor it is achieved that the above-described reduction of the threshold voltage caused by short-channel effects is smaller than for the first transistor, so that the effect of the absence of the halo implantation in the second transistor on the threshold voltage is entirely or partly compensated for.
The channel length of the second transistor can be advantageously chosen to be such that the threshold voltages of the transistors are unequal. A preferred embodiment of a device in accordance with the invention is characterized in that the channel length of the second transistor is such that the threshold voltage of the second transistor is equal, or at least substantially equal, to the threshold voltage of the first transistor.
The invention can be advantageously employed at channel lengths at which a reduction in threshold voltage occurs as a result of short-channel effects. In an important embodiment, the channel length of the first transistor is at the most approximately 0.25 &mgr;m.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 5547894 (1996-08-01), Mandelman et al.
patent: 5618740 (1997-04-01), Huang
patent: 19637105 (1997-04-01), None
Montree Andreas H.
Schmitz Jurriaan
Chaudhuri Olik
Doan Theresa T.
Waxler Aaron
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