Integrated circuit

Details Integrated circuit Integrated circuit

2000-02-10

2002-02-26

Han, Jessica (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S274000

Reexamination Certificate

active

06351109

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an integrated circuit, and more particularly, to an integrated circuit which outputs a reset signal when detecting transition of a power source voltage.
BACKGROUND OF THE INVENTION
A conventional integrated circuit
31
is shown in
FIG. 7
, which serves as a power source detecting circuit for outputting a reset signal upon detection of a rising and a falling of a power source voltage.
As shown in the drawing, resistors R
4
and R
5
are connected in series between a power source line VDD and an earth line VSS, and a connection point (node N
12
) of these two resistors is connected to the gate of an NMOS transistor T
16
. The source of the NMOS transistor T
16
is connected to the earth line VSS, and the drain thereof is connected to the power source line VDD through a resistor R
6
. Also, a connection point (node N
13
) of the NMOS transistor T
16
and resistor R
6
is connected to the gates of a PMOS transistor T
17
and an NMOS transistor T
18
.
The source of the PMOS transistor T
17
is connected to the power source line VDD, and the drain thereof is connected to the drain of the NMOS transistor T
18
, while the source of the NMOS transistor T
18
is connected to the earth line VSS. A connection point (node N
3
) of the PMOS transistor T
17
and NMOS transistor T
18
is a reset terminal from which a reset signal is outputted.
In order to save a standby current consumption of the power source detecting circuit, the resistors employed therein are generally given with large resistance values; For example, in case of the integrated circuit
31
, the resistance values of the resistors R
4
and R
5
are both approximately 54000 k&OHgr; and the resistance value of the resistor R
6
is approximately 75000 k&OHgr;.
The following will explain the operation of the integrated circuit
31
given with relatively large resistance values in cases of fast rising and slow rising power source voltages with reference to timing charts shown in
FIGS. 8 and 9
, respectively. In these drawings, a voltage is used as the ordinate and a time is used as the abscissa, and a broken line represents a power source voltage.
A case of the slow rising power source voltage with the rise time of longer than
1
ms will be explained first. As shown in
FIG. 8
, at start-up of the power source voltage, a voltage at the node N
12
, which shows a value of the power source voltage divided by the resistors R
4
and R
5
, increases as the power source voltage rises. Because the NMOS transistor T
16
stays OFF until the voltage at the node N
12
reaches the threshold of the NMOS transistor T
1
, a voltage at the node N
13
increases as high as the power source voltage through the resistor RG. When the voltage at the node N
13
reaches the threshold of the NMOS transistor T
18
, the PMOS transistor T
17
is switched OFF whereas the NMOS transistor T
18
is switched ON, whereby a voltage at the node N
3
, that is, the reset signal, shifts to a low level from an initial floating state immediately after the power source supply.
Eventually, a voltage at the node N
12
increases and exceeds the threshold of the NMOS transistor T
16
. Then, the NMOS transistor T
16
is switched ON, whereby the voltage at the node N
13
shifts to the low level. Accordingly, the PMOS transistor T
17
is switched ON whereas the NMOS transistor T
18
is switched OFF, whereby the reset signal shifts to a high level from the low level.
Then, while the power source voltage maintains a normal value, the voltage at the node N
3
stays in the high level,. and when the power source voltage starts to drop, the voltage at the node N
3
drops as low as the power source voltage, because the PMOS transistor T
17
stays ON. When the voltage at the node N
12
drops below the threshold of the NMOS transistor T
16
, the NMOS transistor T
16
is switched OFF and the voltage at the node N
13
increases as high as the power source voltage, thereby shifting to the high level. Consequently, the NMOS transistor T
18
is switched ON whereas the PMOS transistor T
17
is switched OFF, whereby the voltage at the node N
3
shifts to the low level.
As has been discussed, in case of the slow rising power source voltage, the integrated circuit
31
detects the rising and falling of the power source voltage, and outputs a pulse of a high-level signal as a reset signal from the reset terminal (node N
3
) while the power source voltage maintains a predetermined value (normal period).
Next, a contrarily case of the fast rising power source voltage with the rise time of shorter than
100
As will be explained with reference to FIG.
9
. As shown in the drawing, at start-up of the power source voltage, an increase of the voltage at the node N
12
is delayed and gradual in comparison with the rising of the power source voltage. Thus, the voltage at the node N
12
stays in the low level longer, during which an increase of the voltage at the node N
13
is also delayed and gradual in comparison with the rising of the power source voltage. Throughout this period, the voltage at the node N
13
keeps increasing, but remains in the low level. Then, when the voltage at the node N
12
exceeds the threshold of the NMOS transistor T
16
, the NMOS transistor T
16
is switched ON, whereupon the voltage at the node N
13
starts to drop further. Accordingly, the NMOS transistor T
18
stays OFF throughout the rising period of the power source voltage, while the voltage at the node N
3
stays in the floating state until the PMOS transistor T
17
is switched ON and then starts to increase as high as the power source voltage when the PMOS transistor T
17
is switched ON.
As has been discussed, in case of the fast rising power source voltage, the reset signal has a potential as high as that of the power source voltage at start-up and starts in the high level. Thus, the integrated circuit
31
can not recognize the low level, and therefore, is unable to control the rising of the rest signal.
Generally, the power source voltage does not fall fast, and for this reason, the voltages at the nodes N
12
, N
13
, and N
3
fall in the same manner as was described in case of the slow rising power source voltage. Thus, the integrated circuit
31
can control the falling of the reset signal.
Other examples of the integrated circuit which outputs a reset signal are disclosed in the following publications. Japanese Laid-open Patent Application No. 258085/1993 (Japanese Official Gazette, Tokukaihei No. 5-258085, published on Oct. 8, 1993) discloses an integrated circuit which can readily output a reset signal in case of either fast or slow rising power source voltage. Japanese Laid-open Patent Application No. 283997/1993 (Japanese Official Gazette, Tokukaihei No. 5-283997, published on Oct. 29, 1993) discloses an integrated circuit having a high voltage source and a low voltage source, so that a malfunction of a circuit operating on a high voltage source is prevented when a voltage in the low voltage source drops. Japanese Laidopen Patent Application No. 326825/1993 (Japanese Official Gazette, Tokukaihei No. 5-326825, published on Dec. 10, 1993) discloses an integrated circuit which stops supply of the power source when the power source voltage drops to or below a predetermined value, so that damages caused by external noise is prevented. Japanese Laid-open Patent Application No. 118019/1986 (Japanese Official Gazette, Tokukaisho No. 61-118019, published on Jun. 5, 1986) discloses an integrated circuit which secures clearing job stability by setting a clearing time for an internal circuit after detecting that the power source voltage has reached the operable lower limit voltage of the internal circuit.
As has been discussed, the conventional integrated circuit
31
can not control the rising of the reset signal in case of the fast rising power source voltage. Thus, a circuit which is to be reset by the integrated circuit
31
may not be initialized properly. Smaller values may be given to the resistors R
4
, R
5
, and R
6
, so that the reset operation is per

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