1991-05-16
1992-07-07
Larkins, William D.
357 71, 357 51, 357 59, H01L 2904, H01L 2348, H01L 2702
Patent
active
051287382
ABSTRACT:
A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connetion between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.
REFERENCES:
patent: 4792841 (1988-12-01), Nagasawa et al
IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1054-1059, "A 7.5-ns 32Kx8 CMOS SRAM," Hiroaki Okuyama et al.
Lee Kuo-Hua
Nagy William J.
Sung Janmye
AT&T Bell Laboratories
Larkins William D.
Limanek Robert
Rebberg John T.
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