Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-05-21
2003-04-29
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185240
Reexamination Certificate
active
06556477
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of integrated circuit (IC) design. Specifically, it relates to an integrated chip having a Static Random Access Memory (SRAM) device, a Dynamic Random Access Memory (DRAM) device and a Flash memory device and a method for fabricating the same. More specifically, it relates to an integrated chip in which the SRAM device is a high resistive load SRAM device, the DRAM device is a deep trench DRAM device, having a deep trench capacitor, and the Flash memory device is a conventional stack-gate Flash memory device.
BACKGROUND OF THE INVENTION
Many applications exist in which a variety of memory devices including SRAM, DRAM and Flash memory devices are used. These are typically integrated into multi-chip packages. Each memory device has its own characteristics, making it suitable for certain types of storage. An SRAM device provides high-speed performance. A DRAM device is more compact than an SRAM device, thereby providing a higher storage capacity. Both SRAM and DRAM devices are volatile memories. A DRAM device requires frequent refresh operations for maintaining storage of valid data when power is down. Refresh operations consume power and interrupt availability of data.
A Flash memory device is nonvolatile. However, read, write and erase operations are slow for a Flash memory device relative to DRAM and SRAM devices. Further, high power is required for erase and write operations (with an erase operation typically being required prior to a write operation) for a Flash memory device relative to DRAM and SRAM devices. Furthermore, a Flash memory device lifetime is limited, typically to a range of 100,000 program/erase cycles.
Each memory device is used in accordance with the advantages and disadvantages inherent to its characteristics. Typically an SRAM device is used as a high-speed L1 cache, a DRAM device is used as a temporary pad or integrated into the system for use as an L2 cache, and a Flash memory device is used for preserving data when power is interrupted. A DRAM device is used as a shadow of a Flash memory device such as for storing data copied from the Flash memory device when power is on to allow high-speed access and to allow updating of application codes stored by the Flash memory device without compromising system performance. Furthermore, a DRAM device is typically used to store volatile data such as system stack, scratch pad variables and frame buffers, etc. Using a DRAM device as a shadow of a Flash memory device extends the lifetime of the Flash memory device since less write/erase operations are performed by the Flash memory device over a given period of time.
There are disadvantages to providing SRAM, DRAM and Flash memory devices in a multi-chip package, as compared to integrating one or more of the memory devices onto a single chip. One disadvantage is that multi-chip packages generally incur higher fabrication costs than a single-chip with an embedded DRAM device. One example is to build DRAM and Flash memory on the same chip. Fabrication cost can be decreased by using a DRAM BIST (Built-In Self-Test) methodology, in which a DRAM macro embedded with a Flash memory macro can be tested at a high speed. Using DRAM BIST methodology, addresses of faulted elements of DRAM devices are recorded by using flash memory which provides a lower cost solution than stand-alone DRAM chips employing fuse banks for redundancy design.
Another disadvantage to multi-chip packages is a degradation of system performance. For example, stand-alone chips are generally limited to a narrow bandwidth, with the I/O datalines being used alternately for input and output. By integrating various memory macros onto one chip, wider internal data bandwidth with a shorter lengthen for communication can be provided. Furthermore, using an embedded DRAM (eDRAM), in which a DRAM macro is integrated onto a CPU chip, a relatively wide bandwidth can be used for two-way communication between the eDRAM and the CPU, as well as the eDRAM and the Flash memory device, significantly improving communication, and thus performance. An eDRAM used as an L2 cache further boosts the system performance.
Integration of memory devices into one chip has been proposed. For example, in U.S. Pat. No. 6,141,242 issued to Hsu et al., entitled “LOW COST MIXED MEMORY INTEGRATION WITH SUBSTANTIALLY COPLANAR GATE SURFACES”, teaches a fabrication process for integrating an SRAM structure having a thin-film transistor, a DRAM structure having a stack capacitor and a Flash memory structure having a three piece floating gate structure onto a single chip. The fabrication process is restricted to use with a specific type of memory device, i.e., a Flash memory structure having a three-piece floating gate structure, whose use is limited.
SUMMARY
An aspect of the present invention is to provide a semiconductor chip including DRAM, SRAM and Flash memory devices fabricated on the same substrate, wherein the memory devices are widely known, and are highly reliable to overcome the disadvantages of the prior art.
Another aspect of the present invention is to provide a semiconductor chip including highly reliable and widely known memory devices including DRAM, SRAM and Flash Memory devices fabricated on the same substrate together with a CPU core
Another aspect of the present invention is to provide an integrated chip having three types of memory devices including a deep-trench DRAM device.
Still another aspect of the present invention is to provide an integrated chip having three types of memory devices including a high density, high resistive load SRAM device.
Another aspect of the present invention is to provide an integrated chip having three types of memory devices including a conventional stack-gate Flash memory.
Also, another aspect of the present invention is to provide a method for fabricating an integrated chip having three types of memory devices including a deep-trench DRAM, a high resistive load SRAM and a conventional stack-gate Flash memory.
Finally, another aspect of the present invention, is to provide a low-cost method for fabricating an integrated chip having three types of memory devices including DRAM, SRAM and Flash memory devices, in which the three memory devices are fabricated simultaneously together with support circuits.
Accordingly, in an embodiment of the present invention, a semiconductor memory device fabricated on one substrate is presented having an NVRAM device, a DRAM device, and an SRAM device having a high resistive load element. In another embodiment the DRAM device is a deep trench DRAM device. In another embodiment the DRAM device is a stack capacitor DRAM device.
In another embodiment of the present invention, a method is presented for fabricating a semiconductor memory device including the steps of providing a single substrate, fabricating an NVRAM, DRAM, and SRAM device on a single substrate, wherein the SRAM device has a high resistive load element. In another embodiment the step of fabricating the DRAM device includes the step of fabricating a deep trench DRAM device. In another embodiment the step of fabricating a DRAM device includes the step of fabricating a stack capacitor DRAM device.
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Hsu Louis L.
Radens Carl
Wang Li-Kong
Dilworth & Barrese LLP
IBM Corporation
Tran M.
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