Integrated charge-pump phase-locked loop circuit

Details Integrated charge-pump phase-locked loop circuit Integrated charge-pump phase-locked loop circuit

1992-10-13

1993-08-03

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 1A, 331 8, 331 25, 328155, H03L 700, H03L 7089, H03L 7107

Patent

active

052333140

ABSTRACT:
A variable bandwidth phase-locked loop clock generator circuit is disclosed. The PLL circuit includes a phase comparator which presents pump-up and pump-down signals, indicating the polarity of the desired frequency change. The phase comparator also generates multiple level control outputs to control the rate of the frequency change. A current source includes a reference leg having a plurality of resistors which are shorted out according to the control outputs, from which a bias signal is generated. The level of the bias signal controls current sources in the output leg of the current source to control the rate of change of the voltage applied to the voltage controlled oscillator. In addition, the bias signal also controls the slew rate of an active low-pass filter according to the desired response characteristic; the output of the filter is applied to the voltage controlled oscillator for generating the output clock signal. This construction of the PLL circuit allows for the control signals to control the rate of change both for advancing and retarding the output clock frequency, and allows for on-chip implementation of the filter components in a manner compatible with MOS technology.

REFERENCES:
patent: 4745372 (1988-05-01), Miwa
patent: 4771249 (1988-09-01), Burch et al.
patent: 4896122 (1990-01-01), Tahernia et al.
patent: 4920320 (1990-04-01), Matthews
patent: 4931748 (1990-06-01), McDermott et al.
Stetzler, "Clock Circuit Design Considerations for High Performance VSLI Processors," (U. Cal., 1985).
"Phase-Locked Loop Design Fundamentals" (Motorola, date unknown).
Gardner, "Phase Accuracy of Change Pump PLL's," IEEE Trans. Commun., vol. Com-30 Oct. 1982), pp 2362-2363.
Johnson et al., "A Variable Delay Line PLL for CPU/Comprocessor Synchronization", IEEE J. Solid State Cir, vol. 23, No. 5 (Oct. 1988) pp. 1218-1223.
Gardner, "Charge-Pump Phase-Lock Loops", IEEE Trans. Commun. vol. Com-28 Nov 1980), pp. 1849-1858.
Jeong, et al., "Design of PLL-Based Clock Generation Circuits", IEEE J. Solid State Cir., vol. SC-22, No. 2 (Apr., 1987), pp. 255-261.

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